Substrate Packaging Research and Development Engineer
$133,800 - $188,890 USD yearly
Part of Intel's Substrate Packaging Technology Development (SPTD) organization supporting heterogeneous integration and die disaggregation.
Originally posted 4 August 2026 by the employer. Relisted by the employer on 11 November 2026.
About the role
This role develops and optimizes substrate packaging processes, materials, and equipment to meet reliability, quality, and cost targets within the Substrate Packaging Technology Development (SPTD) organization. The team focuses on solutions enabling heterogeneous integration and die disaggregation for high-performance and mobile computing applications.
What you'll do
- Develop and optimize advanced packaging processes, materials, and equipment for quality, reliability, and cost targets.
- Design and implement process specifications, workflows, and equipment configurations for new technologies.
- Conduct design of experiments (DOE) to characterize process windows and interactions between equipment, materials, and chemistry.
- Drive continuous improvement efforts to enhance process capability, stability, and productivity.
- Establish material specifications and partner with suppliers to ensure adherence to performance and quality standards.
- Provide sustaining support for equipment performance and process health in high-volume manufacturing environments.
What you'll need
- PhD in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, Organic Chemistry, Polymer Engineering, or a related engineering field, plus 1+ years of related experience.
- Experience combining engineering judgement and data analysis skills to draw conclusions, build models, and design experiments.
- Experience in materials science and engineering, along with material characterization techniques.
- Experience in design of experiments (DOE), statistical data analysis, and statistical process control (SPC).
Nice to have
- Working knowledge or prior experience in optics and lasers, laser micro-machining, and micro-fabrication.
Skills: module engineer, high-volume manufacturing, equipment optimization, process control, yield enhancement, technology transfer
More semiconductor jobs: Intel Corporation jobs · Packaging engineer jobs · Arizona jobs
First seen in our index 197 days ago, well above the 34-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
279
|
Median days since first seen
34 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (279 roles · 46 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 279 |
| Open roles in the wider Process, Fab & Equipment family | 230 | 10225 · 116 employers |
| Median days since first seen | 36 d | 34 d (−2 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: module engineer, high-volume manufacturing, equipment optimization, process control, yield enhancement, technology transfer
Who's hiring in this category
- Infineon Technologies · 38 open roles · median 23 d
- Renesas Electronics · 29 open roles · median 36 d
- Micron Technology · 18 open roles · median 53 d
- onsemi · 16 open roles · median 43 d
- STMicroelectronics · 16 open roles · median 20 d
- SanDisk · 14 open roles · median 12 d
How we counted: 279 open Packaging Engineering (Packaging) roles from 46 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Process, Fab & Equipment family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.