Senior Package Design Engineer - Bayan Lepas, my, Malaysia
Originally posted 29 October 2026 by the employer.
About the role
This role designs and develops package and interconnect methods for Power SiP/modules, flip-chip LGA, multi-chip modules, and power device packaging. Focus areas include power packages for AI/HPC, Vertical Power Delivery (VPD), Server VR core/peripheral, and Accelerator/GPU applications.
What you'll do
- Design and develop package and interconnect methods for Power SiP/modules, flip-chip LGA, multi-chip modules, and power device packaging.
- Collaborate with OSAT and contract manufacturing partners to execute DOEs, optimize assembly processes, and establish process specifications.
- Partner with Product Groups and Reliability engineering teams to qualify new packages and processes within designated project schedules.
- Support production transition by resolving process integration challenges, defining production controls and monitors, and troubleshooting process issues.
- Maintain technical expertise in advanced leadframe, power SiP/modules, and flip-chip interconnect architectures.
- Resolve internal and external customer complaints in alignment with Marketing, Product Groups, Quality, and Operations teams.
What you'll need
- Bachelor's or Master's degree in Physics, Chemistry, Mechanical, Electrical, or Materials Engineering.
- 5-15 years of relevant package development experience emphasizing leadframe, laminate, power SiP/module, flip-chip packaging, and wafer Front-Side (FSM) / Back-Side (BM) Metallization processing.
- Technical understanding of semiconductor power device package assembly processes, materials, and packaging technologies.
- Working knowledge of wafer front-side / backside metallization, wire-bonding, flip chip, multi-chip modules, SPC (Statistical Process Control), and statistical analysis.
- Proficiency in AutoCAD along with standard office productivity applications.
Skills: Package Design, Power SiP, Flip-Chip, DOE, Metallization
More semiconductor jobs: Packaging engineer jobs · Malaysia jobs
This role has been open 0 days — well below the 48-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
242
|
Median days open
48 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (242 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 242 |
| Open roles in the wider Process, Fab & Equipment family | 203 | 10323 · 107 employers |
| Median days open | 38 d | 48 d (−10 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: Package Design, Power SiP, Flip-Chip, DOE, Metallization
Who's hiring in this category
- Renesas Electronics (this employer) · 30 open roles · median 41 d
- Infineon Technologies · 26 open roles · median 41 d
- Micron Technology · 20 open roles · median 78 d
- onsemi · 16 open roles · median 34 d
- Skyworks · 15 open roles · median 2 d
- Intel Corporation · 11 open roles · median 113 d
How we counted: 242 open Packaging Engineering (Packaging) roles from 44 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.