Process Engineer
Responsible for the Underfill (UF) process for flip-chip die-level assembly.
Originally posted 15 September 2026 by the employer.
About the role
This role is responsible for the Underfill (UF) process for flip-chip die-level assembly, supporting Assembly Process Engineering in delivering process and equipment solutions.
What you'll do
- Set up new Underfill processes, materials, and recipes, executing process window studies, Design of Experiments (DOE), and corner limit evaluations.
- Maintain assembly yield and test yield for the Underfill process, establishing golden recipes, lot bracketing, and disposition.
- Lead process qualifications to meet CTQ requirements, CPK targets, risk assessments, UPH, yield, and cost targets.
- Perform root cause analysis and troubleshooting using structured methodologies such as 5M+1E, 5 Whys, DMAIC, and 8D.
- Monitor and optimize Underfill equipment performance, coordinating preventive maintenance and resolving process deviations.
- Develop and maintain process documentation, including work instructions, process specifications, control plans, OCAPs, and technical reports.
What you'll need
- Bachelor's Degree or higher in Engineering (Electrical, Mechanical, Physics, Materials Science, or a related field).
- Minimum 4-5 years of experience in semiconductor assembly process engineering.
- Direct experience in Underfill process development and sustaining.
- Knowledge of semiconductor assembly processes and flip-chip die-level assembly technology.
- Working knowledge of Failure Mode and Effects Analysis (FMEA), Statistical Process Control (SPC), 8D Problem Solving, Six Sigma methodologies, Design of Experiments (DOE), and statistical analysis tools such as Minitab and JMP.
Nice to have
- Familiarity with Nordson dispenser, Heller reflow oven, and C-Scan equipment.
- Knowledge of underfill defect mechanisms such as voiding, fillet irregularities, incomplete fill, delamination, overflow, and package warpage.
- Experience supporting New Product Introduction (NPI), high volume manufacturing (HVM), process transfer, and manufacturing ramp-up activities.
- Familiarity with reliability qualification requirements, including MSL, TCT, HTS, HAST, and board-level reliability testing.
- Familiarity with SEM, SAM (C-Scan), X-ray, and cross-section analysis for failure investigation and process validation.
More semiconductor jobs: SanDisk jobs · Packaging engineer jobs · Malaysia jobs
This role has been open 0 days — well below the 64-day median for Packaging Engineering roles.
Packaging Engineering · Advanced Packaging
|
Open roles in category
297
|
Median days open
64 d
|
Category median salary (all employers)
$167k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (297 roles · 59 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 297 |
| Open roles in the wider Process, Fab & Equipment family | 73 | 10091 · 105 employers |
| Median days open | 0 d | 64 d (−64 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Who's hiring in this category
- KLA Corporation · 41 open roles · median 141 d
- Micron Technology · 41 open roles · median 45 d
- Intel Corporation · 20 open roles · median 54 d
- Renesas Electronics · 17 open roles · median 46 d
- GlobalFoundries · 14 open roles · median 73 d
- Lumilens · 13 open roles · median 84 d
How we counted: 297 open Packaging Engineering (Advanced Packaging) roles from 59 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.