Principal Wafer Bonding Integration Engineer
$160,000 - $220,000 USD yearly
MEMS-based silicon photonics optical circuit switches (OCS)
About the role
The Principal Wafer Bonding Integration Engineer leads the development, integration, and manufacturing transfer of advanced wafer bonding processes for MEMS-based silicon photonics optical circuit switches.
What you'll do
- Own the wafer bonding integration strategy from early product development through high-volume manufacturing.
- Develop and optimize wafer bonding processes, including fusion bonding, eutectic bonding, hybrid bonding, and direct wafer bonding.
- Define bonding process windows, alignment strategies, thermal budgets, surface preparation, CMP requirements, and post-bond processing.
- Serve as the primary technical interface with external foundries for tape-outs, process qualifications, engineering builds, and production ramps.
- Analyze wafer-level metrology and inspection data to lead root cause investigations of bonding defects such as voids, delamination, and alignment errors.
- Drive yield improvement and reliability using statistical process control (SPC) metrics, design of experiments (DOE), and excursion management.
What you'll need
- BS, MS, or PhD in Materials Science, Mechanical Engineering, Electrical Engineering, Physics, MEMS, or a related technical discipline.
- 10+ years of experience in new product introduction with ownership in wafer process integration, advanced packaging, or CMOS manufacturing.
- Hands-on and product development expertise with advanced wafer bonding technologies, including fusion bonding, eutectic bonding, hybrid bonding, or direct bonding.
- Experience with TSV integration, wafer thinning, cavity SOI, or 3D integration technologies.
- Proven track record supporting products through NPI and manufacturing ramp while working directly with semiconductor foundries or external manufacturing partners.
- Strong understanding of SPC, DOE, process characterization, yield improvement, and statistical analysis.
Nice to have
- Experience in MEMS, silicon photonics, advanced packaging, or heterogeneous integration.
- Technical Service Engineering (TSE) experience supporting semiconductor customers or foundries.
- Familiarity with wafer-level metrology techniques, including SEM, IR inspection, profilometry, C-SAM, or AFM.
- Working knowledge of 8D, FMEA, Six Sigma, and structured root cause methodologies.
Skills: wafer bonding, fusion bonding, hybrid bonding, TSV, 3D integration
More semiconductor jobs: Packaging engineer jobs · Santa Clara jobs
This role has been open 0 days — well below the 64-day median for Packaging Engineering roles.
Packaging Engineering · Advanced Packaging
|
Open roles in category
295
|
Median days open
64 d
|
Category median salary (all employers)
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | nEye | All employers we track in this specialty (295 roles · 57 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 295 |
| Open roles in the wider Process, Fab & Equipment family | 5 | 10088 · 116 employers |
| Median days open | 0 d | 64 d (−64 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: wafer bonding, fusion bonding, hybrid bonding, TSV, 3D integration
Who's hiring in this category
- Micron Technology · 42 open roles · median 49 d
- KLA Corporation · 39 open roles · median 145 d
- Intel Corporation · 20 open roles · median 47 d
- Renesas Electronics · 17 open roles · median 50 d
- Lumilens · 13 open roles · median 88 d
- onsemi · 12 open roles · median 48 d
How we counted: 295 open Packaging Engineering (Advanced Packaging) roles from 57 employers tracked in the SemiconductorJobs index, counted 3 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.