$210,000 - $315,000 USD yearly
Support high-speed SerDes electrical model extraction and system-level simulation for computing and server projects.
Originally posted 3 September 2026 by the employer.
About the role
Perform signal and power integrity tasks while partnering with package, platform, and IC designers to optimize package and system designs. The role supports high-speed SerDes electrical model extraction and system-level simulation for high-speed computing and server projects.
What you'll do
- Perform IO analysis using established methodologies, including model extraction, simulation, and reporting across various serial interfaces.
- Analyze IO power distribution for product development and reference systems using established methodologies.
- Perform package extraction for time- and frequency-domain analysis and provide package design guidelines.
- Support high-speed SerDes electrical model extraction and system-level simulation.
- Collaborate with board, package, and IC design teams across organizational boundaries and document results thoroughly.
What you'll need
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ years of System/Package Design/Technology Engineering or related work experience (or Master's degree and 7+ years, or PhD and 6+ years).
- Experience performing electrical model extraction and signal and power integrity simulations.
- Experience with package extraction for time- and frequency-domain analysis.
- Experience with IO analysis for serial interfaces and IO power distribution analysis.
Nice to have
- 10 years of experience with high-speed SerDes package, PCB, or system design for computing/server standards.
- Strong background in electromagnetics, transmission line theory, and crosstalk.
- Proficiency with field solvers such as HFSS, Q3D, Sentinel-PSI, and Clarity, as well as SPICE transient simulation tools such as ADS and HSPICE, including IBIS and IBIS-AMI models.
- Experience with SerDes specifications such as PCIe, USB, UFS, and MIPI.
- Experience using MATLAB to automate simulation workflows.
- Experience with programming languages such as C/C++ or scripting languages such as Perl/Python.
- Master’s or Ph.D. degree with 10 years of industry experience.
Skills: signal integrity, power integrity, HFSS, SerDes, package extraction
More semiconductor jobs: Qualcomm jobs · Packaging engineer jobs · San Diego jobs
First seen in our index 70 days ago, well above the 31-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
288
|
Median days since first seen
31 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (288 roles · 46 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 288 |
| Open roles in the wider Process, Fab & Equipment family | 48 | 10371 · 119 employers |
| Median days since first seen | 75 d | 31 d (−44 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: signal integrity, power integrity, HFSS, SerDes, package extraction
Who's hiring in this category
- Infineon Technologies · 37 open roles · median 24 d
- Renesas Electronics · 33 open roles · median 27 d
- Micron Technology · 18 open roles · median 54 d
- onsemi · 17 open roles · median 44 d
- STMicroelectronics · 16 open roles · median 21 d
- SanDisk · 15 open roles · median 13 d
How we counted: 288 open Packaging Engineering (Packaging) roles from 46 employers tracked in the SemiconductorJobs index, counted 12 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Process, Fab & Equipment family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.