$160,200 - $240,200 USD yearly
Lead package development across 2.5D/3D integration, CoWoS, SoIC, hybrid bonding, and HBM for AI and data center architectures.
Originally posted 12 November 2026 by the employer.
About the role
This role leads package technology development, architecture, NPI, and manufacturing execution for AI and data center products. The work focuses on advanced heterogeneous integration with foundries, OSATs, substrate suppliers, and internal teams.
What you'll do
- Lead package development for 2.5D/3D integration, CoWoS, SoIC, HBM, Silicon Bridge, hybrid bonding, FCBGA, and high-density substrates.
- Drive package architecture optimization including die floorplanning, bump/microbump strategy, power/signal integrity, and thermal/mechanical design.
- Develop package test vehicles to support technology qualification and early risk reduction.
- Lead package NPI from concept through engineering builds, qualification, production ramp, and manufacturing release.
- Drive bumping, flip-chip assembly, underfill, thermal solutions, substrate assembly, and board-level integration.
- Partner with foundries, bumping houses, substrate suppliers, and OSATs on design rules, PDK readiness, process capability, reliability, yield, cycle time, capacity, and production ramp.
What you'll need
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field with 4+ years of System/Package Design/Technology Engineering experience (or Master's with 3+ years, or PhD with 2+ years).
- Experience leading technical risk assessment, root-cause analysis, qualification, yield improvement, and manufacturing readiness.
- Hands-on experience driving package architecture, die floorplanning, and bump/microbump strategies.
- Experience qualifying new processes, production lines, and multi-source manufacturing setups.
Nice to have
- M.S. or Ph.D. in Materials Science, Mechanical engineering, chemical engineering or equivalent.
- Minimum of 8–10 years hands-on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production.
Skills: 2.5D/3D integration, CoWoS, SoIC, hybrid bonding, HBM, bumping
More semiconductor jobs: Qualcomm jobs · Advanced packaging jobs · San Diego jobs
First seen in our index 0 days ago, well below the 48-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
79
|
Median days since first seen
48 d
|
Category median salary (all employers)
$189k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (79 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 79 |
| Median days since first seen | 57 d | 48 d (−9 d vs this employer) |
| Median salary (USD postings) | n/a | $189k |
Skills observed across this category: 2.5D/3D integration, CoWoS, SoIC, hybrid bonding, HBM, bumping
Who's hiring in this category
- AMD · 11 open roles · median 29 d
- Micron Technology · 11 open roles · median 194 d
- Marvell Technology · 7 open roles · median 44 d
- NVIDIA · 6 open roles · median 66 d
- Qualcomm (this employer) · 5 open roles · median 86 d
- Intel Corporation · 4 open roles · median 50 d
How we counted: 79 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 29 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Days are counted from when our index first saw each posting, not from the employer's original posting date.