Packaging Engineer (Substrate Design and Layout, Only open for fresh graduate)
Use Cadence SIP and Allegro for package design and advanced substrate layout in Taichung.
Originally posted 11 September 2026 by the employer.
About the role
This role involves developing package designs and substrate layouts for products. You will use EDA layout tools such as Cadence SIP and Allegro to support package structure evaluations and routing planning.
What you'll do
- Participate in the development of package design and advanced substrate layout for products.
- Use EDA layout tools including Cadence SIP and Allegro to perform package and substrate drawing, design modifications, and related engineering tasks.
- Perform basic routing planning, layer stack-up configuration, and design-for-manufacturability (DFM) checks based on established design rules and manufacturing requirements.
- Collaborate with hardware, manufacturing, and packaging engineering teams to support package structure evaluations, design updates, and issue resolution.
- Organize and prepare technical documentation while following design guidelines and operational procedures.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Materials Science, Mechanical Engineering, Physics, or another related engineering or science field.
- Ability to learn package design workflows, substrate layout methodologies, and relevant EDA tools.
- Ability to organize and prepare technical documentation and follow design guidelines and operational procedures.
- Teamwork and communication skills to collaborate with global teams and interface with external suppliers.
Nice to have
- Coursework, project experience, or internships related to semiconductor packaging, electronics design, PCB/substrate design, or similar areas.
- Experience with EDA or CAD design software such as Cadence, AutoCAD, Altium, or Mentor.
Skills: substrate design, layout, semiconductor packaging, EDA tools, Cadence
More semiconductor jobs: SanDisk jobs · Packaging engineer jobs · Taiwan jobs
This role has been open 0 days — well below the 46-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
250
|
Median days open
46 d
|
Category median salary (all employers)
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (250 roles · 45 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 250 |
| Open roles in the wider Process, Fab & Equipment family | 73 | 10091 · 105 employers |
| Median days open | 0 d | 46 d (−46 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: substrate design, layout, semiconductor packaging, EDA tools, Cadence
Who's hiring in this category
- Renesas Electronics · 31 open roles · median 39 d
- Infineon Technologies · 26 open roles · median 42 d
- Micron Technology · 20 open roles · median 79 d
- onsemi · 15 open roles · median 35 d
- Skyworks · 15 open roles · median 3 d
- Intel Corporation · 12 open roles · median 71 d
How we counted: 250 open Packaging Engineering (Packaging) roles from 45 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.