Packaging Engineer (Substrate Design and Layout)
Design and optimize substrate layouts for ASIC and SiP packaging solutions across SSD/PSSD NAND BGA, uSD, SD/SD express, and USB products.
Originally posted 22 June 2026 by the employer.
About the role
This role is responsible for optimizing die bonding pads, flip chip die plots, and substrate layouts to streamline design complexity and reduce cost for ASIC and SiP packaging solutions. Work encompasses products including SSD/PSSD NAND BGA, uSD, SD/SD express, and USB products.
What you'll do
- Optimize die bonding pads, flip chip die plots, and substrate layouts for ASIC and SiP packaging solutions across SSD/PSSD NAND BGA, uSD, SD/SD express, and USB products.
- Support the development and integration of new platform packaging technologies, new NAND generations, and new ASICs with an emphasis on interposer, substrate, and board co-design.
- Conduct substrate layout feasibility studies, perform die fitment analysis based on playbook guidelines, and prepare design documentation.
- Maintain and manage design libraries while generating accurate bonding diagrams to support layout and assembly processes.
- Interface with assembly houses and substrate vendors to conduct design reviews, verify compliance with design rules, and support manufacturability.
- Support the development of department automation systems.
What you'll need
- Master’s or Bachelor’s degree in Materials Science, Electrical/Electronics Engineering, or a relevant engineering or science discipline.
- Up to 5 years of design experience in semiconductor packaging, substrate design, or related fields.
- Proficiency in EDA tools, including Cadence SiP/Allegro, AutoCAD, CAM, and Valor for substrate and package design.
- Solid understanding of packaging design and manufacturing processes, particularly wire bonding, flip chip, and substrate-based technologies.
- Working knowledge of materials, thermal considerations, package warpage/BLR, and electrical performance principles.
- Familiarity with substrate fabrication and manufacturing workflows, including design rule interpretation and vendor engagement.
Nice to have
- Familiarity with WB version design and advanced packaging technologies such as FCBGA, MCM, or 2.5D designs.
Skills: Cadence SiP, substrate design, FCBGA, wire bonding, package layout
More semiconductor jobs: SanDisk jobs · Packaging engineer jobs · Taiwan jobs
This role has been open 0 days — well below the 46-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
250
|
Median days open
46 d
|
Category median salary (all employers)
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (250 roles · 45 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 250 |
| Open roles in the wider Process, Fab & Equipment family | 73 | 10091 · 105 employers |
| Median days open | 0 d | 46 d (−46 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: Cadence SiP, substrate design, FCBGA, wire bonding, package layout
Who's hiring in this category
- Renesas Electronics · 31 open roles · median 39 d
- Infineon Technologies · 26 open roles · median 42 d
- Micron Technology · 20 open roles · median 79 d
- onsemi · 15 open roles · median 35 d
- Skyworks · 15 open roles · median 3 d
- Intel Corporation · 12 open roles · median 71 d
How we counted: 250 open Packaging Engineering (Packaging) roles from 45 employers tracked in the SemiconductorJobs index, counted 30 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.