Wireless SOC Design Verification Engineer - Irvine, United States
Originally posted 27 October 2026 by the employer.
Apple’s N1 wireless chip powers connectivity across iPhone products.
About the role
Apple is seeking a Wireless SOC Design Verification Engineer to own verification scope end-to-end from test planning through signoff. The role supports Apple's N1 wireless chip successor across blocks and top-level SOC integration.
What you'll do
- Own verification end-to-end from test planning to signoff across the Power Management Unit, CPU subsystem, on-chip debug infrastructure, PCIe, bus fabric, boot and secure-boot sequencing, and peripherals including SPI and UART. - Select and apply simulation, formal verification, or alternative verification methodologies based on design needs. - Verify low-power intent across subsystems using UPF. - Implement AI-assisted verification approaches across test generation, debug, and verification closure. - Deliver full ASIC cycle verification spanning concept, tape-out, and bring-up.
What you'll need
- BS and a minimum of 10 years of relevant industry experience. - Proven track record of working the full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage closure. - Expertise in SystemVerilog coding. - Expertise in UVM methodology.
Nice to have
- Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI-based bus architecture in UVM environment. - Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC. - Experience with Formal Verification. - In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, and HW/FW interaction verification. - Experience taping out large SOC systems with embedded processor cores.
Skills: SystemVerilog, UVM, PCIe, WiFi, Bluetooth SOC
This role has been open 0 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 55 | 1268 |
| Open roles in the wider Digital Design & Verification family | 133 | 3359 · 116 employers |
| Median days open | 7 d | 67 d (−60 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, PCIe, WiFi, Bluetooth SOC
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.