Hardware Engineer, Principal - Newport Beach, CA, United States
Originally posted 4 August 2026 by the employer.
Architect UVM environments and drive verification for complex Ethernet and Microcontroller SOC products.
About the role
MACOM is seeking a Principal Hardware Engineer to independently architect UVM-based verification environments and own verification at the module and full-chip level. The position focuses on developing test plans, test environments, and test suites to verify complex Ethernet and Microcontroller SOC products.
What you'll do
- Specify product verification test plans. - Drive verification methodologies and practices. - Develop SystemVerilog verification IP. - Develop chip-level and block-level test environments, including drivers, monitors, scoreboards, and functional checkers. - Develop and debug test suites covering passing, failing, error, and breaking scenarios. - Lead and mentor other verification engineers on the team.
What you'll need
- Proficiency in SystemVerilog and advanced UVM methodologies. - Experience architecting UVM-based environments and applying functional coverage techniques. - Experience with SystemVerilog assertions. - Experience developing test plans, environments, and test suites for Ethernet and Microcontroller SOC products. - Prior experience working with and guiding junior members of a verification team.
Nice to have
- Prior experience as a verification lead.
Skills: UVM, SystemVerilog, functional coverage, Ethernet, SOC
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1277
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MACOM | All employers we track in this specialty (1277 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1277 |
| Open roles in the wider Digital Design & Verification family | 3 | 3342 · 117 employers |
| Median days open | 0 d | 64 d (−64 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, functional coverage, Ethernet, SOC
Who's hiring in this category
- Qualcomm · 112 open roles · median 42 d
- AMD · 92 open roles · median 57 d
- NVIDIA · 91 open roles · median 67 d
- Synopsys · 73 open roles · median 42 d
- SiFive · 56 open roles · median 81 d
- Apple · 55 open roles · median 8 d
How we counted: 1277 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.