VLSI Design Verification Engineer_2 - Taiwan Hsinchu, Taiwan
Originally posted 16 July 2026 by the employer.
About the role
This role is part of the VLSI Verification team working on SoCs for AI vision processors in edge applications. The position applies verification methodologies including SystemVerilog/UVM, coverage-driven verification, assertion-based verification, and AI-assisted verification tools.
What you'll do
- Develop and execute verification plans for complex SoCs and IPs.
- Build testbenches, assertions, and coverage models.
- Collaborate with architects, designers, and post-silicon teams.
- Ensure correctness and reliability of designs.
What you'll need
- Bachelor’s, Master’s, or PhD in EE, CS, or a related field.
- Background in digital design and computer architecture.
- Experience with SystemVerilog, UVM, Verilog, C, or C++.
- Debugging, analytical, and problem-solving skills.
Nice to have
- Scripting experience with Perl or Python.
Skills: SystemVerilog, UVM, testbenches, assertions, coverage models, VLSI
More semiconductor jobs: Ambarella jobs · Verification engineer jobs · Taiwan jobs
This role has been open 105 days — well above the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1293
|
Median days open
58 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ambarella | All employers we track in this specialty (1293 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1293 |
| Open roles in the wider Digital Design & Verification family | 10 | 3364 · 116 employers |
| Median days open | 105 d | 58 d (+47 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: SystemVerilog, UVM, testbenches, assertions, coverage models, VLSI
Who's hiring in this category
- Qualcomm · 113 open roles · median 42 d
- NVIDIA · 95 open roles · median 67 d
- AMD · 90 open roles · median 58 d
- Synopsys · 74 open roles · median 43 d
- Apple · 69 open roles · median 8 d
- SiFive · 56 open roles · median 82 d
How we counted: 1293 open Design Verification (Design Verification) roles from 98 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.