Validation Engineer – AI & Server Platforms - TX, Austin, United States
Originally posted 22 October 2026 by the employer.
About the role
This role drives system validation and debug of AI GPU systems within the datacenter CPU and AI post-silicon validation team. Focus areas include high-speed IO interfaces such as PCI Express, CXL, and RAS.
What you'll do
- Develop and execute feature enablement and validation test plans for SoC- and system-level SoC features across AMD Server and AI products. - Leverage AI/ML technologies to enhance post-silicon validation, debug, and test automation efficiency, including AI-assisted workflows, data analytics, failure triage, log analysis, and root-cause identification. - Develop test content for focus testing, system-level stress testing of the IO domain, and cross-product stress testing. - Functionally validate, regress, execute, and debug Networking, IFoE, IB, UAL, scale-up, scale-out, or related domains. - Develop post-silicon validation infrastructure encompassing software, hardware, automation environments, and lab setups. - Provide root cause analysis for platform-level, SoC logical, performance, and BIOS/firmware issues in a datacenter environment.
What you'll need
- Bachelor's degree in EE, CSE, or CS with 5+ years of experience, or Master's degree in EE, CSE, or CS with 3+ years of experience. - Domain expertise in IO interfaces including PCIe, CXL, RAS, or Power management for system-level test-plan execution. - Understanding of Server platform components and x86 or other complex CPU architectures. - Experience developing validation test-plans, executing tests, and debugging at the SoC and platform level. - Experience participating in silicon bring-up and debug. - Familiarity with programming or scripting languages including C/C++, Python, or Perl. - Experience with board- and platform-level debug, oscilloscopes, protocol analyzers, and JTAG-based debug tools.
Nice to have
- Proficiency with Linux and/or Microsoft Operating Systems. - Knowledge of pre-silicon environments such as Verification, Emulation, or Virtual Bring-Up.
Skills: Post-Silicon, PCI Express, CXL, Silicon Bring-Up, Debug
This role has been open 0 days — well below the 44-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
414
|
Median days open
44 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (414 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 55 | 414 |
| Open roles in the wider Silicon Validation & Test family | 143 | 2256 · 113 employers |
| Median days open | 41 d | 44 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: Post-Silicon, PCI Express, CXL, Silicon Bring-Up, Debug
Who's hiring in this category
- AMD (this employer) · 54 open roles · median 48 d
- Qualcomm · 38 open roles · median 28 d
- Micron Technology · 37 open roles · median 44 d
- NVIDIA · 25 open roles · median 23 d
- Microchip Technology · 22 open roles · median 73 d
- Graphcore · 21 open roles · median 126 d
How we counted: 414 open Post-Silicon Validation (Silicon Validation) roles from 62 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.