Mgr III, ASIC - AMZ25936.5 - Cupertino, California, United States
$223,641 - $272,400 USD yearly
Originally posted 19 October 2026 by the employer.
About the role
This role leads a team of verification engineers responsible for the functional verification of advanced AI-focused System-on-Chip (SoC) designs at Annapurna Labs. The scope encompasses neural network accelerators, high-speed interconnects, and memory subsystems.
What you'll do
- Lead a team of verification engineers in the functional verification of AI-focused SoC designs, including neural network accelerators, high-speed interconnects, and memory subsystems. - Manage project schedules, deliverables, and performance metrics while mentoring and developing junior engineers. - Define, develop, and implement verification strategies and testplans aligned with AI-specific architectural and performance goals. - Oversee the creation of modular, reusable UVM-based testbenches for verifying compute engines, DMA controllers, and AI-specific processing blocks. - Collaborate with architecture, RTL design, software, and machine learning teams to ensure coverage of functional requirements and performance metrics. - Drive verification closure through coverage-driven verification methodologies, including code, functional, and assertion coverage. - Utilize simulation tools, formal verification techniques, and emulation platforms to validate complex AI workloads and edge-case scenarios.
What you'll need
- Experience managing engineering schedules, deliverables, performance metrics, and leading verification engineers. - Technical background in functional verification of AI-focused SoC designs, including neural network accelerators and memory subsystems. - Expertise developing modular, reusable UVM (Universal Verification Methodology) based testbenches. - Experience achieving verification closure using coverage-driven verification, including code, functional, and assertion coverage. - Hands-on proficiency with simulation tools, formal verification techniques, and emulation platforms.
Skills: ASIC, verification closure, coverage-driven, emulation, formal verification
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 1233 |
| Open roles in the wider Digital Design & Verification family | 23 | 3298 · 115 employers |
| Median days open | 22 d | 64 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC, verification closure, coverage-driven, emulation, formal verification
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.