Test Design Engineer - San Jose, United States
Originally posted 27 October 2026 by the employer.
About the role
As a Test Design Engineer at Etched, you will own the end-to-end test strategy and test systems across silicon bring-up, boards, servers, and full racks from early validation into production.
What you'll do
- Define and own the overall test strategy and coverage map across silicon, firmware, board, server, and rack levels from EVT/DVT/PVT validation through production. - Design test systems and frameworks governing how tests are structured, versioned, gated, and executed across lab and factory environments. - Review domain-team test plans across build phases, identify coverage gaps, eliminate redundant tests, and optimize coverage against test time. - Build regression gating to validate firmware, drivers, and test packages on representative hardware prior to release. - Define pass/fail criteria, retest policies, and diagnostics, coordinating with Production to establish procedures. - Lead root-cause triage across hardware, firmware, and software using logs and lab tools, and partner with manufacturing partners including travel to Taiwan.
What you'll need
- Experience owning the test strategy or test systems for at least one hardware product from bring-up into production. - Hands-on testing experience across low-level firmware, board-level, and system-level testing. - Experience designing regression gating or CI for hardware and firmware. - Debugging skills across hardware, firmware, and software working from logs and lab tools. - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience. - Willingness to work onsite in San Jose and travel internationally to manufacturing partners.
Nice to have
- 8+ years in test engineering, test architecture, system validation, or test automation for hardware products. - Experience with server, rack, GPU, or accelerator systems, including post-silicon bring-up and rack-level (L10/L11) integration testing. - Experience with BMC, BIOS, PCIe, high-speed interconnects, and power and thermal validation. - Experience with hardware-in-the-loop test systems. - Experience with factory test, test stations, or working with contract manufacturers and ODMs. - Experience with yield analysis and data-driven test optimization.
Skills: EVT/DVT/PVT, bring-up, test strategy, regression gating, server validation
This role has been open 0 days — well below the 42-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
427
|
Median days open
42 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Etched | All employers we track in this specialty (427 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 427 |
| Open roles in the wider Silicon Validation & Test family | 11 | 2253 · 112 employers |
| Median days open | 54 d | 42 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: EVT/DVT/PVT, bring-up, test strategy, regression gating, server validation
Who's hiring in this category
- AMD · 51 open roles · median 42 d
- Qualcomm · 37 open roles · median 29 d
- Micron Technology · 36 open roles · median 43 d
- NVIDIA · 24 open roles · median 28 d
- Microchip Technology · 22 open roles · median 79 d
- Apple · 21 open roles · median 5 d
How we counted: 427 open Post-Silicon Validation (Silicon Validation) roles from 63 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.