Template Job - San Jose, California, United States
Originally posted 18 September 2026 by the employer — open 0 days.
Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions.
About the role
This role involves designing and developing layouts for integrated circuits.
What you'll do
- Design and develop integrated circuit layouts following electronics engineering principles.
- Perform floor planning, create layouts of building blocks, and integrate layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes.
- Focus on minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS.
- Manage the manufacturing process of products, including technology yield and performance.
- Develop test programs and procedures to ensure products meet performance specifications.
What you'll need
- Bachelor's degree in electrical engineering.
- 10+ years of experience in the development of layouts for highspeed analog IC designs in fin FET technology.
- Experience with layout extraction tools and analyzing layout parasitic to achieve high quality layout for highspeed circuits.
- EMIR and antenna DRC rules aware layout practices.
- Experience writing SKILL and TCL scripts.
Skills: layout, advanced node CMOS, floor planning, DRC, LVS
This role has been open 0 days — well below the 86-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
680
|
Median days open
86 d
|
Median salary
$197k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (680 roles · 73 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 680 |
| Open roles in the wider Physical Implementation family | 25 | 1386 · 105 employers |
| Median days open | 65 d | 86 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $197k |
Skills observed across this category: layout, advanced node CMOS, floor planning, DRC, LVS
Who's hiring in this category
- Cadence Design Systems · 173 open roles · median 141 d
- Synopsys · 52 open roles · median 58 d
- NVIDIA · 50 open roles · median 90 d
- Micron Technology · 36 open roles · median 119 d
- Qualcomm · 36 open roles · median 72 d
- Intel Corporation · 29 open roles · median 23 d
How we counted: 680 open EDA/CAD Engineering (EDA Tools) roles from 73 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.