SoC Physical Design Engineer, Top Level - Beaverton, United States
Originally posted 21 September 2026 by the employer.
About the role
This role involves implementing complete chip design from netlist to tapeout.
What you'll do
- Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
- Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
- Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route.
- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
What you'll need
- BS degree and 10+ years of relevant industry experience.
- Experience integrating IP from both internal and external vendors and able to specify and drive IP requirements in the physical domain.
- Experience with large SoC designs (>20M gates) with frequencies in excess of 1GHz using sub 45nm technologies.
- A detailed understanding of database management issues.
- Experience with floorplanning tools, P&R flows, global timing verification and physical design verification flows.
Nice to have
- Familiarity with ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, and hard IP integration.
- Experience with SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.
- Familiarity with a hierarchical design approach, top-down design, budgeting, timing and physical convergence.
- Familiarity with various process-related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
Skills: ASIC integration, floorplanning, clock and power distribution, P&R flows, physical design verification
This role has been open 10 days — well below the 58-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
641
|
Median days open
58 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (641 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 641 |
| Open roles in the wider Physical Implementation family | 25 | 1436 · 108 employers |
| Median days open | 14 d | 58 d (−44 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC integration, floorplanning, clock and power distribution, P&R flows, physical design verification
Who's hiring in this category
- Qualcomm · 128 open roles · median 38 d
- AMD · 43 open roles · median 29 d
- Broadcom · 39 open roles · median 81 d
- NVIDIA · 38 open roles · median 56 d
- Synopsys · 27 open roles · median 46 d
- NXP Semiconductors · 24 open roles · median 28 d
How we counted: 641 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.