Technical Staff Engineer - Design (FPGA Fabric)
$91,000 - $232,000 USD yearly
Originally posted 7 August 2026 by the employer.
About the role
Microchip Technology is seeking a Technical Staff Engineer - Design (FPGA Fabric) in San Jose, California, responsible for the design, development, and optimization of the FPGA fabric in advanced and low power FPGA devices. You will work within a circuit design team and collaborate with architecture, ASIC, firmware, verification, and test teams.
What you'll do
- Design and develop FPGA fabric architecture, including interconnect, routing muxes, logic elements, memory blocks, clocking, and other key components.
- Analyze and optimize FPGA fabric architecture for performance, power consumption, area utilization, and related metrics.
- Create and verify circuit schematics and functional Verilog models, comparing them back to SPICE-based models.
- Prepare technical documentation, including specifications, design documents, and test plans, and participate in formal reviews of block specifications.
- Support layout, verification, and timing characterization teams, including designing and verifying circuit blocks outside the FPGA fabric.
- Drive and participate in silicon validation of FPGA fabric blocks for functionality and performance.
What you'll need
- Bachelor's degree in Computer Engineering, Electrical Engineering, or Computer Science.
- 12+ years of experience in custom FPGA fabric design and/or memory circuit design.
- High degree of SPICE simulation proficiency.
- Experience leveraging full custom and mixed-signal design EDA tool sets for parasitic extraction, simulations, and EM/IR analysis.
- Demonstrated competency in scripting, managing simulation queues, data capture, and analysis.
- Proven ability to simulate and analyze yield impact, reliability, and power, and support software model developers.
Nice to have
- Master's degree in Computer Engineering, Electrical Engineering, or Computer Science.
- Experience in analog and full custom design.
- Experience in FPGA or ASIC development.
- Experience in functional verification and timing characterization.
- Experience in low-power design including dual rail, array biasing, and dynamic low power mode switching (sleep, power gating, column array muxing).
- Experience in OCV timing and yield variation analyses using Solido and Monte Carlo.
More semiconductor jobs: Microchip Technology jobs · FPGA engineer jobs · San Jose jobs
This role has been open 83 days — well above the 63-day median for FPGA Design roles.
FPGA Design · RTL Design
|
Open roles in category
106
|
Median days open
63 d
|
Category median salary (all employers)
$163k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (106 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 106 |
| Median days open | 80 d | 63 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $163k |
Who's hiring in this category
- Altera · 37 open roles · median 58 d
- AMD · 13 open roles · median 56 d
- Teradyne · 9 open roles · median 81 d
- Qualcomm · 7 open roles · median 58 d
- Keysight Technologies · 6 open roles · median 11 d
- Microchip Technology (this employer) · 6 open roles · median 79 d
How we counted: 106 open FPGA Design (RTL Design) roles from 25 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.