Design Verification Engineer, Leo Payload FPGA

Focus on developing System Verilog and UVM test environments for networking, signal processing, and satellite bus FPGAs on Project Leo.

About the role

This role is for an FPGA verification engineer on the Leo Production team creating and maintaining verification environments and test suites for FPGA-based subsystems. The position focuses on verifying digital designs for networking functions, signal processing, and control functions within Amazon Project Leo's satellite communication system.

What you'll do

• Assist with the planning, architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog/UVM.
• Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions.
• Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases.
• Create reusable Verification IP to be shared across the organization.
• Participate in the development and deployment of networking and satellite bus FPGAs.
• Mentor junior engineers and support implementing upgrades to verification processes and methodologies.

What you'll need

• Experience creating and maintaining verification environments and test suites for FPGA-based subsystems.
• Hands-on experience developing configurable, self-checking testbenches using System Verilog and UVM.
• Experience with constrained-random, metric-driven verification methodologies and coverage metrics collection and analysis.
• Ability to work on-site out of the office 5 days a week.
• Due to export control laws, candidates must be a U.S. citizen or national, U.S. permanent resident (Green Card holder), or lawfully admitted as a refugee or granted asylum.

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