Originally posted 11 September 2026 by the employer — open 0 days.
Astera Labs provides connectivity solutions integrating CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
About the role
This role involves technical leadership in physical design, driving complex designs from architecture to GDSII. You will contribute to products integrating CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
What you'll do
- Drive multiple complex designs to production from architecture to GDSII.
- Apply expertise in synthesis, timing closure, and formal verification at block and full-chip levels.
- Work with physical design tools and methodologies for technologies 16nm or less, preferably 7nm or less.
- Collaborate with IP vendors for RTL and hard-mac blocks.
What you'll need
- Bachelor’s degree in EE / Computer.
- 6+ years of experience supporting or developing complex SoC/silicon products.
- Hands-on knowledge of synthesis, place and route, CTS, extraction timing analysis/STA, and Physical Verification.
- Proven expertise in synthesis, timing closure, and formal verification.
- Experience with Cadence and/or Synopsys physical design tools/flows.
- Familiarity with System Verilog/Verilog.
- Experience with DFT tools and techniques.
- Scripting skills in python or Perl.
Nice to have
- Knowledge of design for test (DFT), stuck-at and transition scan test insertion.
- Familiarity with DFT test coverage and debug.
- Familiarity with ECO methodologies and tools.
Skills: synthesis, place and route, CTS, timing analysis, GDSII, physical verification
This role has been open 0 days — well below the 57-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
616
|
Median days open
57 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (616 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 616 |
| Open roles in the wider Physical Implementation family | 24 | 1419 · 106 employers |
| Median days open | 88 d | 57 d (+31 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: synthesis, place and route, CTS, timing analysis, GDSII, physical verification
Who's hiring in this category
- Qualcomm · 98 open roles · median 35 d
- NVIDIA · 42 open roles · median 50 d
- Broadcom · 41 open roles · median 60 d
- AMD · 31 open roles · median 46 d
- Synopsys · 28 open roles · median 63 d
- NXP Semiconductors · 23 open roles · median 80 d
How we counted: 616 open Physical Design (Physical Design) roles from 76 employers tracked in the SemiconductorJobs index, counted 11 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.