Tech Lead, Physical Design - Bengaluru, Karnataka, India
Originally posted 11 September 2026 by the employer — open 4 days.
Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions, integrating CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
About the role
This role involves owning and executing end-to-end physical design implementation for complex, high-performance ASIC/SoC designs.
What you'll do
- Own and execute end-to-end physical design implementation for complex, high-performance ASIC/SoC designs.
- Perform physical design activities including Floorplanning, partitioning, Power planning, Placement and optimization, Clock Tree Synthesis (CTS), Routing and post-route optimization, Timing closure, Physical verification, and ECO implementation.
- Perform Static Timing Analysis (STA) and resolve setup/hold timing violations.
- Analyze and address congestion, IR drop, electromigration, and signal integrity.
- Drive PPA optimization while meeting aggressive timing and power targets.
- Develop and maintain automation scripts and flows to improve physical design productivity.
What you'll need
- Bachelor's or Master's degree in Electrical/Electronics Engineering, VLSI, Microelectronics, or a related field.
- Strong understanding of ASIC physical design flows and methodologies.
- Hands-on experience with physical design implementation from netlist to GDSII.
- Good understanding of Floorplanning, Placement, CTS, Routing, STA, Timing closure, and Physical verification.
- Experience with industry-standard EDA tools such as Cadence, Synopsys, or equivalent.
- Strong understanding of CMOS digital design and semiconductor fundamentals.
- Good scripting/programming skills in Tcl, Python, Perl, or Shell.
Nice to have
- Experience working on advanced process nodes and high-performance SoCs.
- Experience with block-level and/or full-chip physical design.
- Experience with multi-voltage/multi-clock designs.
- Knowledge of UPF/low-power design methodologies.
- Experience with IR/EM analysis and signal integrity.
- Experience with physical design automation and flow development.
- Exposure to SerDes, PCIe, CXL, Ethernet, memory interfaces, or other high-speed connectivity technologies.
- Experience taking designs through full physical signoff and tapeout.
Skills: synthesis, place and route, CTS, timing analysis, GDSII, physical verification
This role has been open 4 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
611
|
Median days open
59 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (611 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 611 |
| Open roles in the wider Physical Implementation family | 25 | 1411 · 108 employers |
| Median days open | 96 d | 59 d (+37 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: synthesis, place and route, CTS, timing analysis, GDSII, physical verification
Who's hiring in this category
- Qualcomm · 100 open roles · median 39 d
- Broadcom · 39 open roles · median 64 d
- NVIDIA · 37 open roles · median 39 d
- AMD · 31 open roles · median 50 d
- Synopsys · 27 open roles · median 67 d
- Renesas Electronics · 24 open roles · median 49 d
How we counted: 611 open Physical Design (Physical Design) roles from 76 employers tracked in the SemiconductorJobs index, counted 15 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.