Tech Lead, Analog Mixed Signal Layout - Ho Chi Minh City, Vietnam

Originally posted 29 September 2026 by the employer.

About the role

This role involves the layout of advanced analog and mixed-signal circuits, ensuring performance, matching, and manufacturability for high-speed transceiver applications.

What you'll do

• Perform full-custom layout of high-speed SerDes designs, including RX Front-ends, TX Drivers, PLLs, CDRs, bias circuits, ADCs/DACs.
• Handle layout of high-frequency components with emphasis on parasitic minimization, shielding, and routing symmetry.
• Floorplan and assemble top-level analog/mixed-signal layouts and perform layout integration.
• Work closely with circuit designers to understand schematic intent, matching, symmetry, and parasitic sensitivity.
• Ensure high-quality layout practices to meet DRC, LVS, ERC, and EM/IR signoff in advanced FinFET processes.
• Perform layout-versus-schematic (LVS), design rule checks (DRC), and parasitic extraction (PEX) using industry-standard tools.
• Support post-layout simulation by extracting and delivering clean parasitic netlists (RC).

What you'll need

• Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or related field.
• 7+ years of experience in custom analog or mixed-signal layout in deep-submicron or FinFET processes.
• Strong experience with high-speed SerDes designs, PLLs, ADCs/DACs, power management units.
• Experience handling sensitive matching and noise isolation constraints (e.g., differential pair matching, guard rings).
• Strong experience with tools like Virtuoso Layout Editor, Calibre, PVS, StarRC, Quantus, or similar.
• Strong understanding of semiconductor physics, CMOS fabrication processes, and advanced process nodes (e.g., 7nm and below).
• In-depth knowledge of layout techniques for minimizing parasitics, noise, and ensuring robust circuit operation.
• Experience with layout debugging and tapeout release process.

Skills: AMS Layout, high-speed SerDes, DRC, LVS, Virtuoso