Staff DSP Architect - Santa Clara, CA, United States
$119,620 - $179,200 USD yearly
Originally posted 2 October 2026 by the employer.
About the role
This role involves the system design and development of DSP architectures for high-speed, low-power electrical and optical transceivers using PAM4 and advanced modulation schemes with FEC.
What you'll do
- Architect and simulate advanced DSP systems, defining features, performance targets, and specifications for analog and digital design teams.
- Conduct research in digital signal processing techniques for high-speed SerDes and optical communication channels.
- Prototype algorithms for equalization, adaptation, and forward error correction (FEC), evaluating feasibility and performance.
- Develop and validate DSP algorithms in C++, MATLAB, or Python within a simulation environment.
- Build bit-true models of DSP architectures and collaborate with design and verification teams for accurate hardware implementation.
- Develop/perform behavioral modeling of mixed-signal circuit designs for transceivers.
What you'll need
- Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 3-5+ years of related professional experience OR Master’s/PhD degree in Computer Science, Electrical Engineering, or related fields with 2+ years of experience.
- Completed graduate coursework in at least two of the following areas: Digital Signal Processing, Digital Communications, Information Theory, Coding Theory, Probability Theory.
Nice to have
- R&D experience in Probability Theory, Detection and Estimation Theory, Coding Theory, Digital Communications, or Digital Signal Processing.
- Proficiency in C++, MATLAB, or Python.
- Knowledgeable about typical optical components used in communication systems, including lasers/modulators/filters/photodetectors/TIAs.
- Experience in high-speed DSP, especially FFE/DFE, adaptive filters, Clock and Data Recovery (CDR), forward error correction, Maximum likelihood sequence detection.
- Experience with signal integrity and ADC based wireline transceiver.
- Experience with either direct-detect/intensity modulated or coherent optical communication.
Skills: DSP systems, high-speed SerDes, PAM4, FEC, optical communication
This role has been open 0 days — well below the 75-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
240
|
Median days open
75 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (240 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 240 |
| Open roles in the wider Analog & Mixed-Signal family | 24 | 1383 · 105 employers |
| Median days open | 4 d | 75 d (−71 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Skills observed across this category: DSP systems, high-speed SerDes, PAM4, FEC, optical communication
Who's hiring in this category
- Synopsys · 28 open roles · median 23 d
- AMD · 27 open roles · median 62 d
- Cadence Design Systems · 19 open roles · median 175 d
- Qualcomm · 19 open roles · median 56 d
- Apple · 12 open roles · median 3 d
- Micron Technology · 11 open roles · median 62 d
How we counted: 240 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.