System Signal/Power Integrity Engineer
Originally posted 17 August 2026 by the employer.
This role supports high data rate SerDes applications, up to 400G systems.
About the role
This role involves the design and debug of system-level Signal and Power Integrity for high data rate SerDes applications. You will contribute to projects focusing on measurement-simulation correlation and model development using electromagnetic field solvers.
What you'll do
- Support high data rate SerDes applications - up to 400G systems.
- Perform system level Signal and Power Integrity design trade-offs and debug.
- Collaborate with package, PCB, and silicon designers for measurement-simulation correlation projects.
- Develop models using electromagnetic field solvers, primarily Ansys HFSS and electronic suite.
- Perform and develop VNA/TDR (50GHz+) measurement techniques and correlate with models and simulations.
- Conduct pre-layout and post-layout modeling and simulation to support package and PCB engineering for signal integrity.
What you'll need
- BS +12yrs, MS +10 yrs or PhD +7yrs Electrical Engineering or Physics.
- Experience in Signal integrity for high-speed digital applications.
- Experience in Power integrity.
- Proficiency with EM modeling tools (Ansys HFSS/SIWave/Q3D and Polar).
- Proficiency with circuit simulation tools (Keysight ADS).
- Understanding of laminate design and fabrication techniques and limitations for both package and PCB designs.
- Knowledge of high speed data communications, transmission-line and electromagnetic-field theory, and numerical analysis.
Nice to have
- Experience with Matlab.
- Experience with Cadence APD/Allegro.
- Familiarity with Linux.
- Familiarity with Keysight AEL.
- Understanding of optical/electrical engine concepts and theory of operation (CWDM, OMA).
- Familiarity with optical channel impairments such as chromatic dispersion (CD) and four-wave mixing (FWM).
Skills: SerDes applications, Signal Integrity, Power Integrity, VNA/TDR measurements, electromagnetic field solvers
This role has been open 43 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 42 | 1385 · 107 employers |
| Median days open | 162 d | 76 d (+86 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: SerDes applications, Signal Integrity, Power Integrity, VNA/TDR measurements, electromagnetic field solvers
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.