System Modelling Engineer - Bangalore, India
Originally posted 30 April 2026 by the employer — open 133 days.
This role focuses on end-to-end PHY system modeling for 224Gbps SerDes IP.
About the role
This senior-level role focuses on architecture, modeling, and performance analysis of 224Gbps SerDes IP. You will lead end-to-end PHY system modeling, including electrical channel, transmitter (TX), receiver (RX), equalization strategies, clocking, and jitter/noise analysis.
What you'll do
- Develop end-to-end behavioral models for 224Gbps SerDes PHYs across TX, channel, and RX.
- Build statistical and time-domain system models to evaluate BER, eye margins, and link robustness.
- Define PHY performance budgets (jitter, noise, ISI, crosstalk, insertion loss).
- Model electrical channels including packages, PCBs, connectors, and crosstalk.
- Develop and tune TX FIR, RX CTLE, DFE, and adaptive equalization algorithms.
- Support modeling and interpretation of industry standards (IEEE, OIF), including 224G-related efforts.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field, and 12+ years of relevant experience; or Master's degree and 8+ years of relevant experience; or PhD and 4+ years of relevant experience.
- Proficiency in analog circuit design, including TX/RX blocks and system-level understanding.
- Expertise in architecture modeling and high-speed design techniques.
- Demonstrated ability to model, simulate, and optimize performance, power, and area for analog and mixed signal IPs.
Nice to have
- Strong leadership and collaboration skills.
- Solid analytical and problem-solving abilities.
- Effective communication skills to articulate architectural features and tradeoffs.
Skills: SerDes PHY System Modeling, 224Gbps SerDes IP, electrical channel, transmitter (TX), receiver (RX), equalization strategies
This role has been open 132 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 7 | 217 |
| Median days open | 132 d | 91 d (+41 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes PHY System Modeling, 224Gbps SerDes IP, electrical channel, transmitter (TX), receiver (RX), equalization strategies
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.