System Architect - Santa Clara, California, United States
About the role
This role involves owning the SoC and Product Specification stack for a 1.6T retimer SoC and the AEC product it enables, at 224G/lane PAM4.
What you'll do
- Own the SoC and Product Specification stack for a 1.6T retimer SoC and the AEC product it enables.
- Author and maintain normative specifications that RTL, firmware, software, SI/PI, manufacturing, qualification, and customer engineering teams execute against.
- Represent architecture in hyperscaler and strategic platform customer specification negotiation.
What you'll need
- 12+ years in shipping high-speed interconnect (retimer, gearbox, PHY, AEC, AOC, coherent optics, SerDes-centric networking silicon).
- Prior System Architect, Chief Architect, or Principal Systems Engineer role on a shipping 100G/lane or higher product.
- Direct authorship of at least one product spec and one silicon spec on a shipping product.
- PAM4 link training, FEC, and on-die telemetry fluency at the specification level.
- Experience with DOORS / JAMA / equivalent traceability tooling.
Skills: retimer, PAM4, high-speed interconnect, SerDes, chiplet
This role has been open 90 days — below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Kandou | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 9 | 1317 · 100 employers |
| Median days open | 98 d | 91 d (+7 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: retimer, PAM4, high-speed interconnect, SerDes, chiplet
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.