Synthesis & STA Engineer – High-Speed SerDes - San Jose, California, United States
$160,000 - $200,000 USD yearly
Originally posted 27 October 2026 by the employer.
About the role
As a Synthesis & STA Engineer – High-Speed SerDes, you will take end-to-end ownership of logic synthesis and static timing analysis across the digital portions of mixed-signal SerDes PHY designs. You will drive planning, coordination, and execution supporting connectivity ASICs and SerDes IP at advanced nodes including TSMC 5nm/3nm and below.
What you'll do
- Perform RTL synthesis, driving area, power, and timing optimization for digital controller and DSP blocks within high-speed SerDes PHY designs. - Author, develop, and validate SDC constraints from scratch, including clock definitions, generated clocks, multi-frequency/multi-mode constraints, I/O delays, false paths, multicycle paths, and clock-domain crossing exceptions. - Set up and manage MMMC environments to enable accurate and efficient STA across process, voltage, and temperature (PVT) corners. - Drive timing closure from synthesis through sign-off across digital blocks embedded within analog/mixed-signal SerDes IP and full-chip SoC integration. - Apply advanced sign-off methodologies at TSMC 5nm/3nm and below, including OCV/AOCV/POCV and PVT effects, while utilizing ETM/ILM libraries for hierarchical timing analysis. - Generate and validate timing ECOs, partnering with physical design, analog, and RTL teams for closure on high-speed data-path and clock-path issues.
What you'll need
- Bachelor's degree in Electrical Engineering or Computer Science. - ≥8 years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications. - Strong proficiency in writing and debugging SDC constraints, including clock modeling, generated clocks, clock-domain crossings, and exception handling. - Expertise in STA methodology and timing closure at both block and full-chip level using Synopsys PrimeTime and/or Cadence Tempus. - Knowledge of synthesis, place-and-route, extraction, and equivalence checking flows (Formality/Conformal) in advanced nodes (5nm/3nm and below). - Strong scripting ability in Tcl, Python, or Perl.
Nice to have
- Master's degree in Electrical Engineering or Computer Science. - Direct experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY digital controller and DSP timing challenges. - Understanding of analog/mixed-signal integration concerns, including PLL/DLL/CDR clock structures, level-shifter/isolation cell constraints, and high-speed clocking architectures. - Experience with power-aware synthesis and STA (UPF/CPF flows) and SystemVerilog/Verilog proficiency. - Experience working with IP vendors for RTL and hard-macro integration, including Liberty (.lib), LEF, and behavioral model characterization.
Skills: STA, synthesis, PrimeTime, SDC, SerDes, timing closure
This role has been open 0 days — well below the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 682 |
| Open roles in the wider Physical Implementation family | 24 | 1530 · 112 employers |
| Median days open | 91 d | 66 d (+25 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: STA, synthesis, PrimeTime, SDC, SerDes, timing closure
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.