[India] Senior ASIC Implementation Engineer - Hyderabad Knowledge City, India
Design and implement silicon for the Dynamic Neural Accelerator AI processor IP.
About the role
The Senior ASIC Implementation Engineer is responsible for key ASIC implementation tasks, including synthesis, timing constraints, ECO implementation, STA, power intent validation, lint, power analysis, and CDC/RDC analysis. The role supports silicon design for EdgeCortix's Dynamic Neural Accelerator AI processor IP.
What you'll do
- Run logic and physical synthesis using optimization techniques to generate optimized gate level netlists for timing, area, and power. - Debug timing, area, and congestion issues in physical implementation, collaborating with RTL and physical design teams. - Perform power estimation at RTL and gate level to identify power reduction opportunities. - Run formal verification checks between RTL and gate level netlists, resolving aborts, inconclusive runs, and logic equivalency failures. - Develop timing constraints for RTL-synthesis and PrimeTime-STA across blocks and top-level SoC. - Develop power intent specifications in UPF for multi-Vdd designs and implement complex ECOs using Conformal ECO flow. - Participate in physical design activities from floor planning to P&R.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field. - 4+ years of ASIC design, verification, validation, integration, or related work experience. - Experience with industry standard synthesis tools. - Hands-on experience with checking tools for Lint, CDC, RDC, and CLP. - Understanding of STA fundamentals and SDC writing experience. - Scripting skills in Python, PERL, or TCL.
Nice to have
- 8+ years of ASIC design-related experience with successful tape-outs in advanced process nodes. - Working knowledge of UPF specification and understanding of power planning implications and physical implementation challenges. - Experience with high-speed/low power ASIC design within a Unix environment. - Experience with clock domain crossing techniques and tools. - Hands-on experience in physical design areas including floorplanning, place and route, macro and pin placement, and power planning.
Skills: Logic/Physical Synthesis, Gate Level Netlist, Timing Constraints, Floorplanning, P&R
This role has been open 124 days — well above the 66-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
682
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | EdgeCortix | All employers we track in this specialty (682 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 682 |
| Open roles in the wider Physical Implementation family | 3 | 1530 · 112 employers |
| Median days open | 124 d | 66 d (+58 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Logic/Physical Synthesis, Gate Level Netlist, Timing Constraints, Floorplanning, P&R
Who's hiring in this category
- Qualcomm · 126 open roles · median 49 d
- AMD · 61 open roles · median 29 d
- Intel Corporation · 40 open roles · median 19 d
- Synopsys · 38 open roles · median 41 d
- Broadcom · 37 open roles · median 102 d
- NVIDIA · 37 open roles · median 69 d
How we counted: 682 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.