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NXP Semiconductors

Stage Ingénieur : Évaluation des Outils de Vérification des Transitions de Domaines d'Horloge (CDC) assistés par IA (H/F)

NXP Semiconductors Grenoble, France Internship 19 days ago
Physical Design & EDA

Originally posted 16 September 2026 by the employer — open 2 days.

About the role

This intern role focuses on evaluating AI-assisted tools for Clock Domain Crossing (CDC) verification to improve the efficiency of the design flow.

What you'll do

  • Learn and understand issues related to static checks.
  • Analyze tool features to enhance result quality.
  • Implement solutions to evaluate these features on concrete cases.
  • Develop a method to apply the solution to future projects.
  • Work with static checks tools to configure, interpret results, and deploy solutions.
  • Analyze different tool feature options and implement them in design projects.

What you'll need

  • Master Degree / last year of engineering school in micro-electronics.
  • Knowledge of integrated circuit design process.
  • Good level of English.

Nice to have

  • Knowledge of synthesis activity.

Skills: static verification, CDC, RDC, AI, EDA tools

Market context

This role has been open 2 days — well below the 53-day median for EDA/CAD Engineering roles.

EDA/CAD Engineering · AI EDA Design

Open roles in category
48
Median days open
53 d
Median salary
$205k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How NXP Semiconductors compares in EDA/CAD Engineering hiring
Metric NXP Semiconductors All employers we track in this specialty (48 roles · 20 employers)
Open roles in this specialty 10 48
Open roles in the wider Physical Implementation family 42 1371 · 106 employers
Median days open 47 d 53 d (−6 d vs this employer)
Median salary (USD postings) — $205k

Skills observed across this category: static verification, CDC, RDC, AI, EDA tools

Who's hiring in this category

  • NXP Semiconductors (this employer) · 10 open roles · median 47 d
  • Cadence Design Systems · 6 open roles · median 26 d
  • NVIDIA · 5 open roles · median 58 d
  • Qualcomm · 4 open roles · median 46 d
  • Micron Technology · 3 open roles · median 134 d
  • Synopsys · 3 open roles · median 31 d

How we counted: 48 open EDA/CAD Engineering (AI EDA Design) roles from 20 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Apply now
Grenoble, France
On-site
Internship
19 days ago

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