Staff VLSI Design Engineer (CAD) - Bengaluru, India
Originally posted 22 September 2026 by the employer.
About the role
This role involves the development and evolution of EDA design environments, focusing on analog and mixed-signal CAD flows.
What you'll do
- Develop and validate PV tools and flows, including parasitic extraction, EMIR drop, and substrate noise analysis.
- Design and create layout test structures using Cadence custom IC Virtuoso platform.
- Implement and integrate physical verification flows in a CAD environment.
- Automate flow execution, detect bottlenecks, and triage violations using agentic AI flows.
- Provide operation and support for layout and circuit designers worldwide within the CAD environment.
- Test, validate, and evaluate new tools/methods for quality improvement and automation.
What you'll need
- 7+ years of development experience in Mixed Signal CAD design Flows.
- Expert proficiency in SKILL, Python, Unix, Perl, or TCL.
- Expertise in Cadence Virtuoso suite of tools and Analog Design environment (finesim/PrimeSim).
- Solid understanding of Calibre Physical Verification rule deck (SVRF) and ICV LVS decks.
- Experience with Layout Automation and Utilities development in Cadence SKILL/SKILL++.
- Working knowledge of revision control software (Git, Perforce, Synchronicity).
Nice to have
- Experience with physical verification tools for parasitic extraction (starRC).
Skills: CAD, layout test structures, physical verification tools, parasitic extraction, Cadence Virtuoso, Calibre SVRF/TVF
This role has been open 0 days — well below the 85-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
682
|
Median days open
85 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (682 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 682 |
| Open roles in the wider Physical Implementation family | 5 | 1414 · 108 employers |
| Median days open | 36 d | 85 d (−49 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: CAD, layout test structures, physical verification tools, parasitic extraction, Cadence Virtuoso, Calibre SVRF/TVF
Who's hiring in this category
- Cadence Design Systems · 169 open roles · median 148 d
- Synopsys · 55 open roles · median 62 d
- NVIDIA · 46 open roles · median 67 d
- Micron Technology · 37 open roles · median 118 d
- Qualcomm · 37 open roles · median 64 d
- Intel Corporation · 28 open roles · median 28 d
How we counted: 682 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.