Staff Verification Engineer - Austin, Texas, United States
$191,100 - $258,500 USD yearly
Originally posted 16 June 2026 by the employer.
Verifying high-speed PCIe and CXL sub-systems for advanced silicon test chips on nodes down to 3nm.
About the role
Arm's Solutions Engineering team is looking for experienced engineers to verify the functionality of high-speed IOs at the sub-system level. The role targets sub-system integration and performance verification for PCIe and CXL technologies on advanced silicon test chips, including 3nm nodes.
What you'll do
- Execute sub-system integration verification, IO scenario verification, interoperability verification with Arm and third-party IPs, and PCIe/CXL performance verification. - Review architecture and design specifications to build functional verification strategies and craft detailed test plans. - Develop SystemVerilog, Verilog, and UVM testbenches and tests, and debug test failures and issues. - Develop and improve verification methodologies used by the team. - Collaborate with other teams on design microarchitecture, verification methodologies, and system performance. - Work with project management on schedules and milestones while guiding and supporting junior team members.
What you'll need
- Bachelor's or Master's degree in Computer Science, Electrical/Computer Engineering, or a similar field with 5+ years of experience in design or verification of PCIe or CXL subsystems or SoCs. - Solid understanding of digital hardware design and Verilog HDL. - Experience in PCIe, CXL, and IDE feature verification and performance analysis. - Experience working with PCIe and CXL IPs, emulation-friendly transactors, and simulation and emulation platforms. - Expertise in UVM-based verification alongside test plan creation and verification strategy development. - Knowledge of formal methodology and debugging using standard debuggers.
Nice to have
- Experience with Arm-based designs and/or Arm system architectures. - Clock domain crossing verification. - Power-aware verification. - Experience with Perl, Python, or other scripting languages.
Skills: UVM, SystemVerilog, PCIe, CXL, sub-system level
This role has been open 120 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 1233 |
| Open roles in the wider Digital Design & Verification family | 104 | 3298 · 115 employers |
| Median days open | 107 d | 64 d (+43 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, PCIe, CXL, sub-system level
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.