Staff Test Engineer - Austin, Texas, United States
$198,100 - $268,000 USD yearly
Originally posted 23 October 2026 by the employer.
About the role
The Staff Test Engineer defines, develops, validates, and deploys secure provisioning flows for semiconductor manufacturing on ATE. This role owns manufacturing execution across wafer sort, final test, SLT, and high-volume manufacturing, covering eFuse/OTP programming, secure debug control, and device identity provisioning.
What you'll do
- Own test enablement for upcoming silicon projects, covering ATE strategy, Advantest 93K hardware configuration, SmarTest 8 program structure, datalogging, and manufacturing readiness. - Drive first-silicon bring-up on ATE, including triage, silicon/ATE debug, characterization execution, correlation, and handoff to CP, FT, SLT, OSAT, and HVM release. - Define and implement ATE characterization plans across voltage, frequency, temperature, process, functional content, HSIO margins, structural coverage, binning strategy, and guardbands. - Develop and maintain ATE test methods, flows, pattern conversion infrastructure, and production test content for functional, HSIO, ATPG/Scan, MBIST, PHY BIST, DC, leakage, and IDDQ test types. - Guide ATE test hardware development with vendors and OSATs, including probe cards, load boards, sockets, thermal interfaces, signal integrity, and power delivery. - Collaborate with Design, DFT, Firmware, Product Engineering, ATE suppliers, and OSATs to resolve complex issues and deliver production-ready test solutions.
What you'll need
- 8+ years of experience in semiconductor manufacturing, ATE test development, product engineering, silicon bring-up, characterization, or production release for complex SoCs, CPUs, AI accelerators, or chiplet-based devices. - Hands-on expertise in Advantest 93K ATE test program development, including SmarTest 7 / SmarTest 8, tester hardware, digital patterns, test methods, debug flows, and binning. - Experience in test architecture and HSIO test and debug, covering PCIe, UCIe, DDR, SerDes, PHY BIST, bench-to-ATE correlation, oscilloscopes, and BERTs. - Understanding of functional testing, structural test integration, DFT concepts, silicon fabrication process, packaging, product qualification, and HVM release requirements. - Demonstrated ownership of end-to-end project execution from architecture through first silicon bring-up, characterization, CP/FT deployment, OSAT release, and yield debug.
This role has been open 0 days — well below the 37-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
581
|
Median days open
37 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (581 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 581 |
| Open roles in the wider Silicon Validation & Test family | 21 | 2320 · 114 employers |
| Median days open | 0 d | 37 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Who's hiring in this category
- Teradyne · 74 open roles · median 33 d
- Infineon Technologies · 46 open roles · median 41 d
- Renesas Electronics · 46 open roles · median 27 d
- Qualcomm · 32 open roles · median 40 d
- Micron Technology · 29 open roles · median 44 d
- Texas Instruments · 29 open roles · median 35 d
How we counted: 581 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.