Staff SOC Physical Design Engineer - Austin, Texas, United States of America, United States
$152,360 - $210,000 USD yearly
Originally posted 15 September 2026 by the employer — open 5 days.
About the role
This individual leads and performs complex responsibilities within the Physical Design Flow for system-on-chip (SoC) products, focusing on target power utilization and optimization.
What you'll do
- Lead, plan, and perform complex responsibilities within the Physical Design Flow of high-speed DDR and graphics.
- Focus on target power utilization and optimization for SoC products, considering impact on power and performance.
- Perform Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis, and closure.
- Conduct various physical verification checks such as LVS, DRC, design-for-manufacturing, and design-for-yield at chip and block levels.
- Provide schedules and support cross-functional engineering efforts to achieve signoff closure for tapeout.
- Contribute at design reviews and project meetings, communicating and implementing development plans.
What you'll need
- Master's Degree in Electrical Engineering, Computer Engineering, Computer Science or a related field.
- Three (3) years of experience in Physical Design Flow, high-speed DDR, graphics, physical verification flows, micro-architecture, SOC algorithm design and modeling, and methodology.
- Experience with Floor Planning.
- Experience with Clock Tree Synthesis.
- Experience with Place and Route.
- Experience with PDN.
- Experience with Timing analysis and closure.
- Experience with physical verification checks (LVS, DRC, design-for-manufacturing, design-for-yield).
Skills: Physical Design Flow, DDR, Floor Planning, Clock Tree Synthesis, Timing analysis
This role has been open 4 days — well below the 59-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
604
|
Median days open
59 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (604 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 108 | 604 |
| Open roles in the wider Physical Implementation family | 148 | 1373 · 107 employers |
| Median days open | 42 d | 59 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Physical Design Flow, DDR, Floor Planning, Clock Tree Synthesis, Timing analysis
Who's hiring in this category
- Qualcomm (this employer) · 108 open roles · median 42 d
- NVIDIA · 39 open roles · median 44 d
- Broadcom · 38 open roles · median 69 d
- AMD · 35 open roles · median 39 d
- Synopsys · 27 open roles · median 58 d
- Renesas Electronics · 25 open roles · median 46 d
How we counted: 604 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.