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AMD

Staff Silicon Design Engineer - SerDes Validation

AMD SG, Singapore Full-time 3 months ago
Analog & Mixed-Signal Design

About the role

This role involves post-silicon validation, characterization, and optimization of high-speed SerDes interfaces across multiple generations of AMD products.

What you'll do

  • Perform post-silicon validation of high-speed SerDes.
  • Understand industry requirements and specifications for high-speed IO.
  • Develop validation methodologies for new industry standards.
  • Characterize the latest SerDes designs.
  • Debug SerDes issues with designers on Silicon.
  • Generate specifications based on measured results.

What you'll need

  • Experience in high-speed IO SerDes post-silicon validation.
  • In-depth knowledge of industry standards such as PCIe, Display Port, JESD, SDI, OIF-CEI-11G/25G/56G/112G-VSR/SR/MR/LR, IEEE 802.3 KR/CR/CAUI/GAUI.
  • Strong programming/scripting skills in Python, C/C++, TCL for firmware development, test methodology development, and test automation.
  • Extensive experience with lab equipment including BERT, analyzers, oscilloscopes, PNA/VNA.
  • Knowledge of SerDes general architectures and link level system analysis.
  • Bachelor's or Master's degree in Computer Engineering/Electrical Engineering.

Nice to have

  • Experience in system level serial link analysis and simulation, system performance optimization, and standard/architecture level study using tools such as MATLAB, ADS.

Skills: SerDes validation, high speed IO, PCIe, industry standards, post-silicon validation

Market context

This role has been open 64 days — well below the 89-day median for High-Speed IO/SerDes Design roles.

High-Speed IO/SerDes Design · Serdes Highspeed

Open roles in category
215
Median days open
89 d
Median salary
$184k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How AMD compares in High-Speed IO/SerDes Design hiring
Metric AMD Market (215 open roles · 44 companies)
Open roles in category 24 215
Median days open 60 d 89 d (−29 d vs this employer)
Median salary (USD postings) — $184k

Skills observed across this category: SerDes validation, high speed IO, PCIe, industry standards, post-silicon validation

Who's hiring in this category

  • AMD (this employer) · 24 open roles · median 60 d
  • Cadence Design Systems · 19 open roles · median 152 d
  • Qualcomm · 18 open roles · median 68 d
  • Synopsys · 16 open roles · median 52 d
  • Broadcom · 11 open roles · median 141 d
  • Micron Technology · 9 open roles · median 126 d

Based on 215 open roles at 44 companies in our index. Snapshot 9 Sept 2026.

Apply now
SG, Singapore
On-site
Full-time
3 months ago

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