Staff Physical Design Engineer: CPU Implementation & Flow Automation - Bengaluru, Karnataka, India
Originally posted 28 September 2026 by the employer.
About the role
This role is responsible for developing and perfecting the RTL-to-GDS implementation flow for high-performance CPU cores. You will take ownership of advanced implementation recipes, driving PPA (Power, Performance, Area) closure on N3/N2 process nodes.
What you'll do
- Develop, validate, and deploy production-ready RTL-to-GDS recipes using Synopsys Fusion Compiler.
- Drive block-level and hierarchical PPA closure, utilizing advanced techniques in timing-driven placement, CTS, and routing.
- Deploy ML optimization tools (DSO.ai) to automate design space exploration and achieve optimal PPA results.
- Provide technical support for flow and tool-related issues, collaborating with the methodology team.
- Create and maintain robust Tcl/Python scripts to improve flow efficiency and ensure repeatable, predictable results.
What you'll need
- 7+ years of experience in Physical Design/Methodology with a focus on high-performance digital implementation.
- Proven experience with FinFET nodes (N5/N3).
- Expert knowledge of the Synopsys digital implementation suite (Fusion Compiler, ICC2, PrimeTime, StarRC).
- Strong understanding of hierarchical physical design, including floorplanning, pin assignment, and timing budgeting.
- High proficiency in Tcl and Python for flow customization and data analysis.
- A track record of solving complex timing and congestion issues in high-speed, high-density CPU blocks.
Nice to have
- Understanding of N2/GAAFET challenges.
Skills: RTL-to-GDS implementation, PPA optimization, FinFET nodes, Synopsys Fusion Compiler, ML optimization tools
This role has been open 0 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
624
|
Median days open
63 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (624 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 624 |
| Open roles in the wider Physical Implementation family | 15 | 1403 · 108 employers |
| Median days open | 25 d | 63 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: RTL-to-GDS implementation, PPA optimization, FinFET nodes, Synopsys Fusion Compiler, ML optimization tools
Who's hiring in this category
- Qualcomm · 113 open roles · median 39 d
- AMD · 41 open roles · median 27 d
- NVIDIA · 38 open roles · median 52 d
- Broadcom · 37 open roles · median 77 d
- Synopsys · 27 open roles · median 66 d
- NXP Semiconductors · 26 open roles · median 76 d
How we counted: 624 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.