Staff PCB Layout Engineer - Chandler, Arizona, United States
$198,100 - $268,000 USD yearly
Originally posted 9 October 2026 by the employer.
About the role
Arm's Hardware Platforms team is seeking a Staff PCB Layout Engineer to create layouts for physical hardware development platforms used to evaluate Arm's custom system-on-chip (SoC) and reference designs. These platforms support software development and validation activities for both external partners and internal development teams.
What you'll do
- Collaborate with hardware design teams across multiple projects to develop complex designs, including footprint creation, component placement, power plane optimization, and routing of high-speed parallel and serial signals based on mechanical and thermal requirements. - Finalize board designs to deliver data packs comprising ODB++, Gerber files, fabrication and assembly drawings, and bills of materials (BOMs). - Advise chip packaging teams on pinout and routing topologies for high-density SoCs, cost optimization, and layer trade-off analysis. - Execute escape routing for high-density SoCs and FPGAs, including estimating routable IO counts for specified stack-ups and rule sets. - Collaborate with PCB fabricators and CEMs to support DFM/DFT and automated assembly aligned with supplier capabilities. - Participate in design reviews and provide technical guidance on design rules, PCB fabrication, and substrate technologies.
What you'll need
- Experience designing complex, impedance-controlled multi-layer (>20), conventional, and HDI PCBs with high pin-count devices (>2000), high-speed interfaces (PCIe and DDR), differential pairs, and high-current PDNs. - Proficiency with EDA tools, specifically Cadence OrCAD CIS and Allegro PCB. - Practical understanding of Signal Integrity and Power Integrity as applied to routing strategies. - Knowledge of conventional and sequential PCB fabrication processes, IPC standards, stackup topologies, substrate materials, via structures, and design rules. - Experience collaborating with chip packaging teams on SoC pinout definitions and escape routing.
Nice to have
- Certified Interconnect Designer (CID, CID+) certification. - Experience with schematic entry for symbol creation and updating schematics from design reviews. - Experience automating decoupling capacitor optimization, IC placement optimization, or design templates.
This role has been open 0 days — well below the 53-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · AI ML Hardware
|
Open roles in category
1022
|
Median days open
53 d
|
Median salary
$155k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1022 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 1022 |
| Open roles in the wider Software, Firmware & Systems family | 132 | 6391 · 148 employers |
| Median days open | 0 d | 53 d (−53 d vs this employer) |
| Median salary (USD postings) | — | $155k |
Who's hiring in this category
- Intel Corporation · 76 open roles · median 40 d
- KLA Corporation · 63 open roles · median 54 d
- Teradyne · 58 open roles · median 40 d
- Applied Materials · 49 open roles · median 68 d
- NVIDIA · 49 open roles · median 71 d
- AMD · 43 open roles · median 57 d
How we counted: 1022 open Hardware Systems Engineering (AI ML Hardware) roles from 100 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.