Staff Package Design Engineer
Originally posted 5 June 2026 by the employer. Relisted by the employer on 4 November 2026.
About the role
This role guides the architecture and physical design of semiconductor packages, covering 2.5D/3D heterogeneous integration, chiplet-based architectures, high-density interposers, and advanced substrate technologies. Technical focus spans cross-domain co-design and defining packaging design rules and methodologies for multi-die integration assignments.
What you'll do
- Lead package layout architecture and physical design for heterogeneous integration, including 2.5D/3D chiplet packaging, high-density interposers, bridge technologies, RDL, and advanced FCBGA solutions.
- Define, establish, and optimize package design rules and assembly Best Known Methods (BKMs) while partnering with foundries, substrate vendors, and OSATs to evaluate DRCs and manufacturing limits.
- Act as the technical focal point across SI/PI, thermal, tooling, and platform integration teams, balancing pin budgets against electrical and mechanical trade-offs.
- Manage the package design cycle, including footprint assignment, stack-up structures, high-speed escape routing, power/ground distribution, and manufacturing release outputs like Gerber/drill data, bump maps, and assembly drawings.
- Provide technical mentorship and guidance to package design engineers while establishing standardized CAD workflows and layout techniques.
What you'll need
- Bachelor's or Master's degree in Mechanical Engineering, Electrical Engineering, Microelectronics, Materials Science, or a related technical discipline.
- 8+ years of related experience with a Bachelor’s degree, 6+ years with a Master’s degree, or 5+ years of R&D experience in advanced 2.5D/3D heterogeneous packaging establishing new design rules and BKMs.
- Technical background in advanced substrate-based packages, flip-chip layout, multi-die/chiplet-based architectures, thermal mitigation, and high-density routing.
- Proficiency with industry-standard package design tools, specifically Siemens/Mentor Xpedition (Layout / Substrate Integrator), Valor NPI, or Cadence Allegro Package Designer / SiP Layout.
- Working understanding of SI/PI fundamentals, impedance control, and crosstalk mitigation.
- Experience leading multi-disciplinary test vehicle or product design meetings and securing tooling/supplier approvals.
Skills: package layout design, FCBGA, SiP, multi-chip modules, substrate and RDL layouts
More semiconductor jobs: Renesas Electronics jobs · Advanced packaging jobs
This role has been open 151 days — well above the 89-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
41
|
Median days open
89 d
|
Category median salary (all employers)
$223k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (41 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 41 |
| Median days open | 150 d | 89 d (+61 d vs this employer) |
| Median salary (USD postings) | — | $223k |
Skills observed across this category: package layout design, FCBGA, SiP, multi-chip modules, substrate and RDL layouts
Who's hiring in this category
- Marvell Technology · 6 open roles · median 53 d
- Micron Technology · 5 open roles · median 154 d
- AMD · 4 open roles · median 47 d
- Intel Corporation · 4 open roles · median 48 d
- NVIDIA · 4 open roles · median 83 d
- Qualcomm · 4 open roles · median 119 d
How we counted: 41 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 4 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.