Staff NPI Package Design Engineer - Hsinchu, Taiwan
Originally posted 23 July 2026 by the employer — open 49 days.
About the role
This Staff NPI Package Design Engineer role involves challenging design and layout in a high-volume environment, supporting Amps, Codecs, and DSPs.
What you'll do
- Design package layouts, stack-ups, drawings, models, simulations, and design documentation.
- Drive package designs that meet Cirrus performance, reliability, and manufacturability requirements.
- Interface with cross-functional teams to define package requirements from electrical, thermal, and mechanical points of view.
- Utilize AutoCAD, GDS tools, Siemens Fast3D, and Cadence SiP Layout to complete physical design, electrical simulation, and manufacturing validation solutions.
- Drive continuous improvement processes for accuracy between the interface of the package to the die and PCB.
- Collaborate with cross-functional teams to establish and maintain design rules for WLCSP, wire bond, and other packages.
What you'll need
- B.S. or higher degree in Mechanical or Electrical Engineering.
- 5-10 years’ experience designing for manufacturability.
- Experienced Cadence SiP layout user.
- Strong AutoCAD user.
- Knowledge of packaging technologies, materials, package substrate design, and assembly rules.
- Understanding of electrical simulation results on a package design.
Nice to have
- Conversant with PCB and Die mechanical layout tools (e.g., Siemens Xpedition, Allegro PCB, Cadence Virtuoso).
- Electrical simulation skills.
- Experience using Siemens Fast 3D.
- Experience using Siemens Calibre DR.
Skills: package designs, die bump array/BGA integration, WLCSP, wire bond, SiP Layout
This role has been open 49 days — well below the 72-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
39
|
Median days open
72 d
|
Median salary
$222k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (39 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 39 |
| Median days open | 49 d | 72 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $222k |
Skills observed across this category: package designs, die bump array/BGA integration, WLCSP, wire bond, SiP Layout
Who's hiring in this category
- Qualcomm · 5 open roles · median 72 d
- AMD · 4 open roles · median 42 d
- Marvell Technology · 4 open roles · median 107 d
- Micron Technology · 4 open roles · median 119 d
- NVIDIA · 4 open roles · median 31 d
- Amazon · 2 open roles · median 17 d
How we counted: 39 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.