Staff Memory Systems Design Engineer - Bengaluru, India
Originally posted 12 August 2026 by the employer.
Design PCIe systems for NVMe SSD products.
About the role
This Staff Memory Systems Design Engineer role involves owning the end-to-end PCIe system design for an NVMe SSD product line across client laptops and enterprise servers. The scope covers PHY/MAC review through ASIC/SoC integration, PCIe SFR/register analysis, and firmware design guidelines for robust link training, link transitions, and low-power behavior.
What you'll do
- Own system-level PCIe Gen5/Gen6 architecture from an NVMe SSD endpoint perspective.
- Define and review PCIe + NVMe integration across SSD products.
- Review and define requirements for PHY + MAC IP integration.
- Own SoC/ASIC integration including clocks, resets, power domains, straps, lane mapping, and sidebands.
- Define PCIe SFR and provide firmware guidelines for flow control, LTSSM observability, power states, and error handling.
- Define sequencing rules for Link & low power transitions, including DLRM, L1, L1SS, L0p, ASPM, clock-down, and APST Coordination.
- Lead platform bring-up and debug activities like enumeration, speed negotiation, width detection, and error recovery.
What you'll need
- Deep expertise in PCIe configuration and extended capability registers (Link, power management, MSI/MSI-X, AER, BARs, L1SS).
- Experience with PHY/MAC/controller IP criteria for Gen5/Gen6 readiness, equalization, margining hooks, lane mapping, SRNS/SRIS tolerance, clocking modes, and power management support.
- Ability to specify platform-facing requirements for retimer/redriver compatibility.
- Experience integrating PCIe subsystem with clocking (REFCLK handling, clock request gating), resets (PERST#, internal resets, FLR), power domains, and sidebands.
- Experience defining lane policy for x4 typical NVMe, lane reversal/polarity, and width detection/recovery.
- Expertise in defining a clean SFR map for firmware control/observability of LTSSM, link speed/width, low-power triggers, clock request/gating behavior, and error logging.
- Experience providing firmware runbooks for link training failures, width reduction, speed fallback, and AER floods.
- Experience with platform interoperability across client (aggressive power policies, fast resume) and enterprise (stable performance, error containment) environments.
Skills: PCIe Gen5/Gen6, NVMe SSD, PHY + MAC IP, SoC/ASIC integration, Link & low power transitions
This role has been open 48 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 6 | 1385 · 107 employers |
| Median days open | 28 d | 76 d (−48 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: PCIe Gen5/Gen6, NVMe SSD, PHY + MAC IP, SoC/ASIC integration, Link & low power transitions
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.