Staff Layout Engineer – DPG Layout - Hyderabad - Phoenix Aquila, India
Originally posted 2 April 2026 by the employer — open 161 days.
About the role
This role involves owning the physical implementation of critical analog, mixed-signal, and custom digital blocks, including both block-level and full-chip layout ownership. You will lead layout implementation using AI-assisted and automated workflows.
What you'll do
- Own the development and physical implementation of critical analog, mixed-signal, and custom digital blocks.
- Lead layout implementation using AI-assisted and automated workflows, applying copilot-based assistants and agentic AI flows.
- Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks.
- Develop and deploy AI-enabled methodologies for semi-automated floorplanning, parasitic estimation, and layout consistency checks.
- Guide and mentor engineers in Analog layout fundamentals, Automation-first approach, Design-for-quality and design-for-yield practices.
- Collaborate closely with Design, CAD, Verification, Reliability, and Program Management teams.
What you'll need
- 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes.
- Strong expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands-on ownership of verification closure.
- Proven experience in layout of critical analog blocks, including Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps.
- Hands-on experience with memory layouts, including DRAM, SRAM, CAM, OTP and understanding of array-to-periphery integration.
- Deep understanding of analog layout fundamentals, including Matching and symmetry, EM, latch-up, coupling, crosstalk, IR-drop, shielding, guard-ring strategies, parasitic effects.
- Proven expertise in defining, developing, and scaling AI-driven automation and AI-assisted methodologies for complex layout workflows.
Skills: analog layout, mixed-signal, custom digital, Cadence Virtuoso, DRC/LVS, memory layouts
This role has been open 138 days — well above the 66-day median for Analog IC Design roles.
Analog IC Design · Analog Design
|
Open roles in category
259
|
Median days open
66 d
|
Median salary
$156k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (259 roles · 46 employers) |
|---|---|---|
| Open roles in category | 33 | 259 |
| Median days open | 45 d | 66 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $156k |
Skills observed across this category: analog layout, mixed-signal, custom digital, Cadence Virtuoso, DRC/LVS, memory layouts
Who's hiring in this category
- Micron Technology (this employer) · 33 open roles · median 45 d
- Texas Instruments · 30 open roles · median 111 d
- NXP Semiconductors · 15 open roles · median 65 d
- Renesas Electronics · 14 open roles · median 53 d
- onsemi · 13 open roles · median 111 d
- Semtech · 11 open roles · median 83 d
How we counted: 259 open Analog IC Design (Analog Design) roles from 46 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.