Staff High-Speed I/O Test Engineer - Mountain View, CA, United States
$187,000 USD yearly
Originally posted 14 July 2026 by the employer.
About the role
You will validate and architect package and system-level test strategies for high-speed I/O interfaces on Lightmatter's product line. Responsibilities include setting up and executing high-speed electrical characterization, driving link bring-ups, and stress-testing I/Os in system environments.
What you'll do
- Execute high-speed serial I/O characterization and validation across multiple platforms. - Architect test concepts, test platforms, and design-for-test rules alongside architecture, signal integrity, and silicon design teams. - Set up and operate high-speed lab equipment including oscilloscopes, BERTs, AWGs, TDRs, and VNAs/PNAs. - Develop Python-based test software and scripts to automate lab measurements, test execution, data analysis, and parameter extraction. - Define and develop stress testing methodologies to identify design operating limits of serial I/Os post-system integration. - Troubleshoot complex issues with compliance test hardware, fixtures, software, and the Device Under Test (DUT).
What you'll need
- Master’s in Electrical Engineering, Computer Engineering, or a related field. - 6+ years of industry experience in transceiver, SerDes, or high-speed link test development on products. - Hands-on lab experience with high-speed equipment, including oscilloscopes, BERTs, PPGs, VNAs, and spectrum analyzers. - Familiarity with high-speed interfaces and analog building blocks such as PLL, CDR, CTLE, DFE, FFE, and FEC. - Experience in test system automation and data processing using Python. - Analytical and debugging skills to resolve hardware and signal integrity issues during test execution.
Nice to have
- Hands-on experience in the characterization and testing of silicon photonics components and circuits, including tunable lasers, power meters, polarization synthesizers, or OBR/OVA. - Understanding of silicon photonics components and optical testing methodologies. - Knowledge of system-level SerDes design and channel analysis, including insertion loss, return loss, crosstalk, and link training algorithms. - Knowledge of industry specifications such as IEEE 802.3, OIF, PCIe, or USB4. - Ph.D. with 2+ years of relevant industry experience.
This role has been open 97 days — well above the 32-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
556
|
Median days open
32 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Lightmatter | All employers we track in this specialty (556 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 556 |
| Open roles in the wider Silicon Validation & Test family | 9 | 2229 · 113 employers |
| Median days open | 36 d | 32 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 78 open roles · median 26 d
- Renesas Electronics · 45 open roles · median 25 d
- Infineon Technologies · 42 open roles · median 41 d
- Micron Technology · 28 open roles · median 36 d
- Qualcomm · 28 open roles · median 32 d
- Texas Instruments · 23 open roles · median 27 d
How we counted: 556 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.