Design Verification Engineer - Sunnyvale, United States
Originally posted 20 October 2026 by the employer.
About the role
As a Design Verification Engineer on the wireless silicon development team, you will design and implement C tests for wireless SoC verification and power analysis.
What you'll do
- Design and implement C tests for wireless SoCs verification and power analysis. - Develop complex tests or power vectors in assembly or C according to test plans. - Collaborate across engineering disciplines to support functional chip design efforts.
What you'll need
- Bachelor's degree. - Experience with C/C++/assembly programming and Verilog/SystemVerilog. - Understanding of C compilation flow and makefile. - Verification skills in constrained random testing and debugging. - Solid understanding of reusable verification framework. - Knowledge of digital logic design, chip architecture, and microarchitecture.
Nice to have
- MSEE degree. - Knowledge of industry standard interfaces. - Understanding of ARM V7 or V8 architecture and CPU architecture and instruction sets. - Experience in setting UVM/System TB with embedded C tests. - Experience in system level tests with Python or other scripting language. - Experience in UVM DV and porting simulation tests to emulation. - Knowledge of wireless protocols.
Skills: UVM, SystemVerilog, constrained random, C/C++, ARM
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1214
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1214 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 34 | 1214 |
| Open roles in the wider Digital Design & Verification family | 96 | 3244 · 116 employers |
| Median days open | 5 d | 64 d (−59 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, SystemVerilog, constrained random, C/C++, ARM
Who's hiring in this category
- Qualcomm · 113 open roles · median 40 d
- AMD · 96 open roles · median 53 d
- NVIDIA · 84 open roles · median 61 d
- Synopsys · 65 open roles · median 35 d
- SiFive · 55 open roles · median 77 d
- Cadence Design Systems · 50 open roles · median 119 d
How we counted: 1214 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.