Staff High-Speed Analog Designer
Originally posted 25 August 2026 by the employer — open 16 days.
Work on multi-Gbps NRZ and PAM4 SerDes IP in the latest FinFET nodes.
About the role
This role involves designing analog circuits to meet power, area, and performance targets in advanced process nodes for multi-Gbps NRZ and PAM4 SerDes IP.
What you'll do
- Design and develop analog sub-blocks for multi-Gbps NRZ and PAM4 SerDes IP, including equalizers, samplers, drivers, VCOs, PLLs, DLLs, ADCs, DACs, and serializers/deserializers.
- Review SerDes standards and translate them into block-level specifications that balance power, area, and performance across the latest FinFET process nodes.
- Identify and refine circuit architectures, evaluating multiple topologies and making design decisions that account for layout constraints, process variation, and reliability.
- Oversee physical layout implementation, working closely with layout engineers to minimize parasitics, manage device stress, and ensure robust matching and ESD protection.
- Develop simulation strategies using SPICE simulators, Verilog-A behavioral models, and scripting (TCL, Perl, Python, MATLAB) to verify circuit performance across corners and conditions.
- Present simulation data and design reviews to peers and customers, documenting design features, test plans, and tradeoffs.
What you'll need
- Bachelor's degree with 6+ years of relevant experience or Master's degree with 4+ years of relevant experience in Electrical Engineering, Computer Engineering, or a related field.
- Deep transistor-level circuit design experience with strong CMOS design fundamentals and hands-on work in advanced process nodes.
- Detailed design experience with at least one SerDes sub-circuit (receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, VCO, phase mixer, DLL, PLL, bandgap reference, ADC, DAC) and familiarity with several others.
- Proficiency with SPICE simulators and simulation methods, including corner analysis, Monte Carlo, and aging simulations.
- Working knowledge of Verilog-A for analog behavioral modeling, simulation control, and data capture.
- Experience with schematic entry, physical layout, and design verification tools.
Nice to have
- Hands-on layout experience with high-speed circuits.
- Familiarity with scripting languages such as TCL, Perl, Python, C, or MATLAB for automation and data analysis.
Skills: SerDes IP, NRZ, PAM4, VCOs, PLLs, FinFET
This role has been open 1 day — well below the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 217 |
| Open roles in the wider Analog & Mixed-Signal family | 25 | 1317 · 100 employers |
| Median days open | 53 d | 91 d (−38 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SerDes IP, NRZ, PAM4, VCOs, PLLs, FinFET
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys (this employer) · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.