Staff - HIG HBM Architecture

Focus on PHY-adjacent and base-die mixed-signal circuits for High Bandwidth Memory (HBM) architectures.

Originally posted 4 August 2026 by the employer. Relisted by the employer on 29 October 2026.

About the role

As part of the High Bandwidth Memory (HBM) team, this role supports the development of analog and mixed-signal circuitry used in memory PHYs and supporting infrastructure. The work focuses on design, simulation, and validation of mixed-signal and PHY-adjacent circuit blocks alongside system-level verification and silicon bring-up.

What you'll do

• Support design and integration of PHY-adjacent and base-die mixed-signal circuits, including schematic implementation and simulation.
• Develop and maintain behavioral models using Verilog-A/AMS real-number modeling or SystemVerilog to support system-level verification.
• Perform block-level SPICE and mixed-signal simulations, analyzing waveform behavior and corner-case scenarios.
• Assist with validation activities including parasitic modeling, verification plan support, and calibration and adaptability checks.
• Collaborate with multi-functional teams to support integration, simulation debug, and silicon bring-up readiness.

What you'll need

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 5 years' experience in analog or mixed-signal design, verification, or PHY-adjacent development.
• Strong understanding of device and circuit fundamentals including MOS behavior, biasing, gain, stability, and digital logic basics.
• Familiarity with industry tools such as Cadence Virtuoso, Spectre, HSPICE, Xcelium/AMS, or VCS/Verdi.
• Fundamental understanding of digital design concepts, including finite-state machines (FSMs), clock-domain crossing (CDC), reset synchronization, and pipelined architectures.
• Familiarity with RTL verification methodologies using SystemVerilog and exposure to UVM-based verification environments.

Nice to have

• Familiarity with Verilog-A/AMS, real-number modeling, or post-layout concepts such as parasitic extraction and analysis.
• Exposure to statistical or Monte Carlo simulation techniques and mixed-signal verification workflows.
• Experience with memory interfaces, HBM architectures, or mixed-signal IP integration through coursework or internships.
• Exposure to high-speed interface concepts including clocking, jitter, termination, sensing, and calibration.
• Background in lab bring-up, silicon debug, or simulation-to-silicon correlation.
• Programming or scripting experience such as Python or MATLAB for automation and data analysis.

Skills: mixed-signal circuits, Verilog-A/AMS, SPICE, high-speed interface, HBM architectures

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