Staff Engineer - Post-Silicon Validation and Characterization
This role involves validating high-speed die-to-die (UCIe) interconnects.
About the role
This role involves the end-to-end testing, characterization, and failure analysis strategy for complex multi-die packages, covering high-speed die-to-die (UCIe) interconnects, Power Delivery Networks (PDN/PMIC), Platform Management Controllers (PMC), and PCIe/CXL subsystems.
What you'll do
- Define development test strategies, coverage targets, content architecture, and traceability from architectural requirements to validation evidence.
- Write low-level C and Python test suites, including bare-metal exercisers, traffic generators, stress patterns, and custom firmware drivers/hooks.
- Build robust test frameworks featuring instrument control, automated sequencing, structured result capture, and Hardware-in-the-Loop (HIL) CI/CD integration.
- Develop lab-to-ATE correlation test suites and drive handoffs to Product & Test Engineering (PTE).
- Build minimally invasive fault-injection hardware/software infrastructure.
- Execute rigorous error campaigns targeting CRC retries, lane degradation/repair, sideband timeouts, PCIe AER, DMA/IOMMU translation faults, and PMIC reset conditions.
What you'll need
- 8–10+ years in post-silicon validation, system software testing, silicon bring-up, or development test for complex SoCs / ASICs / GPUs.
- Advanced proficiency in C and Python for low-level bare-metal test content, hardware abstraction, and automation frameworks.
- Proven experience with Shmoo plotting PVT corner testing, jitter/margin analysis, and guard-band definition.
- Hands-on experience building or executing error-injection and recovery validation campaigns on production silicon.
- Fluency with oscilloscopes, protocol analyzers (PCIe/CXL), logic analyzers, BERTs, thermal chambers, controllable power supplies, and JTAG debuggers.
- Practical, protocol-level understanding of high-speed serial interfaces (PCIe, CXL, or UCIe) and control buses (I2C, SPI, UART, PMBus, SMBus).
- Solid grasp of system power delivery, including sequencing, PMIC telemetry, DVFS, voltage regulation, and protection trip limits.
- Competency with toolchains (Git, CMake, GCC/Clang, CI pipelines) and statistics/data analysis over test populations.
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- AI coding and automation tool usage.
More semiconductor jobs: Post-silicon validation jobs · India jobs
This role has been open 47 days — well below the 64-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Design Verification
|
Open roles in category
133
|
Median days open
64 d
|
Category median salary (all employers)
$194k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | TYLsemi | All employers we track in this specialty (133 roles · 34 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 133 |
| Open roles in the wider Silicon Validation & Test family | 1 | 2395 · 121 employers |
| Median days open | 47 d | 64 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $194k |
Who's hiring in this category
- Qualcomm · 19 open roles · median 51 d
- AMD · 16 open roles · median 77 d
- NVIDIA · 15 open roles · median 88 d
- Arm Holdings · 9 open roles · median 11 d
- Graphcore · 9 open roles · median 144 d
- Micron Technology · 6 open roles · median 216 d
How we counted: 133 open Post-Silicon Validation (Design Verification) roles from 34 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.