Staff Engineer, PCIe PHY/Link Analysis - San Jose, California, United States
$163,000 USD yearly
Originally posted 21 August 2026 by the employer.
This role focuses on the host interface firmware layer intersecting system software and flash management firmware.
About the role
This Staff Engineer role focuses on the host interface firmware layer that sits in the intersection of system software and flash management firmware, driving Samsung's V-NAND technology.
What you'll do
- Understand PHY/Link architecture, implementation, and integration of the PCIe protocol stack from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer.
- Own LTSSM behavior, link training and equalization sequencing, PCIe enumeration, and configuration-space flows during device bring-up.
- Analyze and validate TLP/DLLP handling, flow control, credit management, ordering rules, ACK/NAK and replay, error handling (AER), and end-to-end data integrity.
- Analyze and debug complex PHY, Link, and Transport layer issues during bring-up and sustaining stages of NVMe SSD products, covering protocol (LTSSM / PCIe enumeration) and PCIe feature-related issues.
- Participate in and support industry PHY/Link compliance tests, including PCI-SIG events.
- Provide onsite support for PHY/Link related tasks at customer sites and labs.
What you'll need
- BS in Computer/Electrical/Electronic Engineering or Computer Science with 8+ years, or MS with 5+ years of relevant experience in hardware.
- Deep proficiency with the PCIe protocol spanning the entire architecture from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer.
- Strong hands-on knowledge of LTSSM, link training/equalization, PCIe enumeration, flow control, replay/retry, and error handling (AER).
- Working knowledge of PHY-layer operation (CDR to Equalizer such as VGA, CTLE, DFE, FFE, DSP) sufficient to root-cause link issues.
- Solid experience in C/C++ for embedded systems, and expertise with UART/JTAG/ICE debuggers and general firmware debugging techniques.
- Strong experience with PCIe protocol analyzers, logic analyzers, and signal analyzers for link and transaction-level debug.
Nice to have
- Knowledge on SI/PI for PCIe.
- Proficiency in NVMe, CXL, or SAS/SATA protocols.
- Experience in both pre-silicon and post-silicon SoC validation.
- Experience with PCIe power management (ASPM, L1 substates) and low-power link states.
Skills: PCIe PHY/Link Analysis, PCIe protocol stack, Physical Layer (PHY), Data Link Layer, LTSSM behavior, link training
This role has been open 39 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 5 | 1385 · 107 employers |
| Median days open | 185 d | 76 d (+109 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: PCIe PHY/Link Analysis, PCIe protocol stack, Physical Layer (PHY), Data Link Layer, LTSSM behavior, link training
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.