Staff Engineer, High-Speed I/O Analog-Mixed Circuit - San Jose, California, United States
$163,000 USD yearly
Originally posted 29 January 2026 by the employer — open 223 days. Relisted by the employer on 29 July 2026.
Memory IO’s vision is to provide memory interface technology solutions which can be adopted in HBM, DDR, LPDDR, GDDR, and more.
About the role
This role involves hands-on analog circuit design and verification, with a focus on memory interface technology solutions. You will contribute to memory interface technology solutions for HBM, DDR, LPDDR, and GDDR.
What you'll do
- Perform analog circuit design, including simulation and verification.
- Guide and supervise layout floor-planning activities for optimal performance.
- Own circuit and system specifications.
- Document designs and simulation results.
What you'll need
- 10+ years experience with a BS, 8+ years with an MS, or 5+ years with a PhD in Electrical Engineering or Computer Science.
- 5+ years of experience with system on chip architecture, high-speed serial interfaces, analog and mixed-signal circuit designs using advanced CMOS technology nodes.
- Prior experience in the design of DDR, LPDDR, GDDR, or HBM I/O interfaces.
- Expertise in providing and understanding layout requirements of high speed circuits.
- Knowledge of DLL, PLL, FFE, CTLE, DFE, output drivers, ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design, and low power design.
- Experience working closely with device/process teams to define transistor specs.
- Experience in high frequency clock distribution design, implementation, and analysis.
- Deep understanding of PPA (performance, power, and area) trade-offs.
- Ability to handle EDA tools such as Cadence, MATLAB (Simulink), and EM tools.
- Experience on silicon bring-up and automatic measurement using script.
- Strong scripting and automation skills using Tcl/Perl.
Nice to have
- Knowledge of Python.
Skills: analog circuit design, mixed-signal designs, DDR, LPDDR, GDDR, memory interface technology
This role has been open 165 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 114 d | 91 d (+23 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: analog circuit design, mixed-signal designs, DDR, LPDDR, GDDR, memory interface technology
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.