Staff Engineer, ASIC IP STA - Bengaluru, India
Originally posted 24 September 2026 by the employer.
About the role
This role involves post-layout STA signoff and timing closure for high-speed interface IPs. The focus is on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, and IO Expander.
What you'll do
- Perform post-layout STA signoff and timing closure of high-speed interface IPs.
- Collaborate with IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration.
- Conduct MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes.
- Develop, validate, and debug timing constraints, including clocks, generated clocks, timing exceptions, and mode-specific constraints.
- Generate and validate Liberty (.lib) and ETM timing models, ensuring high-quality timing collateral.
- Support verification teams with SDF generation, validation, and Gate-Level Simulation (GLS).
What you'll need
- 6-10 years of experience in Static Timing Analysis (STA) with 4+ successful tapeouts.
- Expertise with Cadence Tempus.
- In-depth experience in MMMC timing analysis and closure.
- Experience working on high-speed Memory Interface IPs such such as DDR PHY, ONFI PHY, IO Expander (IOE), or similar high-performance interface designs.
- Strong understanding of timing constraints development, validation, and debug.
- Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment.
- Hands-on experience with SDF generation, validation, and Gate-Level Simulation (GLS) support.
- Solid understanding of setup/hold analysis, recovery/removal checks, pulse-width verification, OCV/AOCV/POCV methodologies, and SI-aware timing signoff.
- Experience with Cadence digital implementation and signoff flow, including Genus, Innovus, and Tempus.
- Proficiency in TCL and/or Python for timing analysis, methodology development, and flow automation.
Nice to have
- Experience with advanced-node, high-frequency designs including LPDDR/DDR, ONFI, IO Expander, or similar memory and interface IPs.
- Exposure to AMS/Digital-on-Top IP development flows and timing signoff challenges associated with mixed-signal integrations.
- Familiarity with AI-powered EDA solutions, Agentic AI workflows for design automation and productivity enhancement.
Skills: post-layout STA signoff, timing closure, high-speed interface IPs, Cadence Tempus, MMMC timing analysis
This role has been open 0 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
630
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (630 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 630 |
| Open roles in the wider Physical Implementation family | 75 | 1417 · 108 employers |
| Median days open | 65 d | 61 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: post-layout STA signoff, timing closure, high-speed interface IPs, Cadence Tempus, MMMC timing analysis
Who's hiring in this category
- Qualcomm · 123 open roles · median 37 d
- NVIDIA · 39 open roles · median 48 d
- Broadcom · 38 open roles · median 73 d
- AMD · 35 open roles · median 43 d
- Synopsys · 27 open roles · median 62 d
- Cadence Design Systems · 23 open roles · median 87 d
How we counted: 630 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.