Staff DFT Engineer - Austin, Texas, United States
$198,100 - $268,000 USD yearly
Originally posted 24 August 2026 by the employer.
About the role
Arm's Solutions group DFT team implements DFT for SOC designs across client, datacenter, automotive, and IOT lines of business from early investigation through tape-out and silicon characterization on ATE.
What you'll do
- Architect, implement, and validate DFT techniques on SOCs and sub-systems. - Insert DFT logic into SoC and sub-system levels and validate all DFT features using industry standard simulation tools. - Run RTL as well as unit delay and timing annotated gate level simulations. - Generate ATPG patterns and debug coverage issues to meet targets. - Develop and validate design-for-test timing requirements, review timing reports, and provide fixes. - Collaborate with multi-functional teams to support DFT RTL level insertion, synthesis, scan insertion, place-and-route, and static-timing-analysis. - Participate in ATE targeted test patterns, validation, silicon debug, and silicon characterization.
What you'll need
- Bachelor's or Master's degree in Electronic Engineering, Computer Engineering, or a related field. - 10+ years of experience in Design for Test. - Core DFT expertise including Siemens DFT tools, Streaming Scan Network (SSN), scan compression and insertion, Memory BIST and repair schemes, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level verification, silicon debug, or memory and scan diagnostics. - Experience coding Verilog RTL, TCL, and/or Perl. - Experience with Cadence and/or Synopsys DFT and simulation tools.
Nice to have
- Familiarity with SoC style architectures including multi-clock domain and low power build practices. - Familiarity with Arm IP including Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug. - Background in high performance build, implementation, and DFT timing constraints. - Experience in datacenter chips. - Experience with 2.5D and 3D test.
This role has been open 0 days — well below the 57-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
249
|
Median days open
57 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (249 roles · 54 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 249 |
| Open roles in the wider Digital Design & Verification family | 118 | 3384 · 117 employers |
| Median days open | 45 d | 57 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 36 open roles · median 49 d
- Qualcomm · 25 open roles · median 82 d
- NVIDIA · 21 open roles · median 46 d
- NXP Semiconductors · 19 open roles · median 41 d
- Synopsys · 16 open roles · median 31 d
- Intel Corporation · 10 open roles · median 56 d
How we counted: 249 open DFT Engineering (DFT Test) roles from 54 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.