Staff Design Verification Engineer - Plano, United States
Originally posted 21 October 2026 by the employer.
Verify mixed-signal automotive power management ICs using Real Number Modeling (RNM) and AMS flows.
About the role
As a mixed-signal verification engineer, you will be responsible for the verification and modeling of mixed-signal automotive power management devices, including PMICs, switching regulators, and related analog IP.
What you'll do
- Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration for PMIC designs. - Develop and implement verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards including ISO 26262 and AEC-Q200. - Lead debugging activities for analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces. - Set up, optimize, and debug Gate-Level Simulation (GLS) flows, correlating with RTL simulation results across PVT corners. - Collaborate with cross-functional Design, Application Engineering, ATE, and Silicon Validation teams to debug analog and digital domain interactions. - Maintain verification documentation, test plans, and coverage metrics while evaluating verification tools, methodologies, and infrastructure.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, or a related field. - 8+ years of experience in mixed-signal or analog circuit verification. - Hands-on experience with Real Number Model (RNM) and AMS (Analog Mixed Signal) model integration. - Proficiency in RTL and behavioral simulation tools such as Spectre and Xcelium, alongside Verilog, SystemVerilog, and/or SPICE-based languages. - Expertise in Gate-Level Simulation (GLS) flows and debugging analog blocks (switched-mode regulators, LDO, bandgap, reference circuits) and digital RTL. - Experience with automotive PMIC or power management IC design and verification, alongside verification methodologies including UVM, assertions, and coverage-driven verification.
Skills: mixed-signal, PMIC, UVM, AMS, RNM, Gate-Level Simulation
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 31 | 1233 |
| Open roles in the wider Digital Design & Verification family | 82 | 3298 · 115 employers |
| Median days open | 23 d | 64 d (−41 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: mixed-signal, PMIC, UVM, AMS, RNM, Gate-Level Simulation
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.