Staff Design Verification Engineer - Network Coherent Interconnect - Austin, Texas, United States
$198,100 - $268,000 USD yearly
Originally posted 7 October 2026 by the employer.
Verify the Arm NI-700 Non-Coherent Network-on-Chip Interconnect (NCI) using SystemVerilog, UVM, and AMBA5 CHI protocols.
About the role
Arm is seeking a Staff Design Verification Engineer to verify interconnect products within the System IP team in Austin, Texas. The role focuses on verification for interconnect IP such as the Arm NI-700 Non-Coherent Network-on-Chip Interconnect (NCI) optimized for Armv8 and Armv9 processors.
What you'll do
- Specify, create, and debug SystemVerilog and UVM constrained-random testbenches for System IP interconnects. - Verify complex multiprocessing microarchitectures with a focus on cache coherence and bus protocols including AMBA5 CHI, AMBA4 ACE, and AXI. - Apply software engineering principles, including object-oriented programming, data structures, and algorithms, to develop robust verification environments. - Develop scripts using Python or Perl to automate verification workflows and regressions. - Collaborate with IP and SoC design teams across the product verification cycle.
What you'll need
- Bachelor’s, Master’s, or PhD in Electrical/Computer Engineering or Computer Science. - 8+ years of experience in verification or RTL design. - Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g., AMBA5 CHI, AMBA4 ACE, or AXI). - Previous experience in specification, creation, and debug of SystemVerilog/UVM constrained-random testbenches. - Proven software engineering skills, including understanding of object-oriented programming, data structures, and algorithms. - Excellent knowledge of scripting languages such as Python or Perl.
Nice to have
- Experience in Formal Verification testbenches.
Skills: SystemVerilog, UVM, AMBA5 CHI, cache coherence, constrained-random
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1277
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1277 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 1277 |
| Open roles in the wider Digital Design & Verification family | 118 | 3384 · 117 employers |
| Median days open | 78 d | 64 d (+14 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, AMBA5 CHI, cache coherence, constrained-random
Who's hiring in this category
- Qualcomm · 112 open roles · median 42 d
- AMD · 92 open roles · median 57 d
- NVIDIA · 91 open roles · median 67 d
- Synopsys · 73 open roles · median 42 d
- SiFive · 56 open roles · median 81 d
- Apple · 55 open roles · median 8 d
How we counted: 1277 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.